Router Entry routes vs Spin2

[Christian-B]

@rowleya says
OK, so SpiNNaker 2 routers are more complicated than we thought... it appears that the memory for links and the memory for cores are separate. There is then an additional bit in the link part which identifies if there are any cores to look at and then only processes the cores if it is set. So links is 8 bits per entry and cores is 152 bits per entry.

This might mean that the translation from PACMAN to machine needs to be even more machine-specific

That isn't to say that we can't keep a bit field to represent it overall, just that when it comes to making final tables, they are going to have to do different things with those bits. Note that this could be part of SCAMP as well, i.e. we send 160-bit routes to SCAMP and SCAMP separates them.

[Christian-B]

vec2mesh (1).txt

[Christian-B]

First thought is split the spinnaker_route vector map into two values links and processors.

Everything but the part that sends it to the cores can be the same.

The send to core needs to e version specific

[Christian-B]

personally if we can avoid needing scamp that would be better!

[rowleya]

It is definitely possible to directly programme the router from host without SCAMP involvement, since this is just a memory write. However the key and mask part of the routes, being based on TCAM memory, is write-only so once written you can't read it back for verification! On SpiNNaker 1, SCAMP held a copy of the routing table so that it could be read back when required. This still doesn't need to go through SCAMP of course since any memory can be written from host, although some care is required to ensure it doesn't get written by more than one thing at-a-time.

Having a mechanism at this point that can write routing tables directly is reasonable; it is unlikely to require huge changes to make that work via SCAMP if required.

[rowleya]

Some more info on addresses and routes:

The route0 register is where the link bits are written, which is available at memory address 0x60000, which means that route0[0] is at 0x60000 and route0[1] is at 0x60001 and so on. Note however that these must be written in words, so all the links for routes 0-3 at the same time written as a word to 0x60000 then all the links for routes 4-7 written to 0x60004 and so on.

The route1 register is where the processor bits are written, which is available at memory address 0x80000. The processors for each route are separated into 8-word segments (though only 5 are needed for the 152 bits) for ease of access. So route1[0] is at 0x80000 and route1[1] is at 0x80020 and so on. These will of course be written sequentially in reality since we can only write 32-bits at a time. I don't think it is necessary to write the 3 unused words, but also it doesn't break anything to do so (e.g. writing blocks of entries fully is OK).