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RTL8168.cpp
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RTL8168.cpp
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/*
* RTL8168.cpp - Hardware methods for RealTek RTL8168 family chips
* RealtekR1000SL
*
* Created by Chuck Fry on 10/8/09.
* Copyright 2009 Chuck Fry. All rights reserved.
*
* This software incorporates code from Realtek's open source Linux drivers
* and the open source Mac OS X project RealtekR1000 by Dmitri Arekhta,
* as modified by PSYSTAR Corporation.
*
* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
* copyright PSYSTAR Corporation, 2008
* 2006 (c) Dmitri Arekhta ([email protected])
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
* Realtek 2012, adopted by Slice
*/
#include "RealtekR1000SL.h"
#include "impl_defs.h"
// **********************************
//
// Static Data Member Initialization
//
// **********************************
const u16 RealtekR1000::rtl8168_intr_mask =
SYSErr | LinkChg | RxDescUnavail | TxErr | TxOK | RxErr | RxOK;
const u16 RealtekR1000::rtl8168_napi_event =
RxOK | RxDescUnavail | RxFIFOOver | TxOK | TxErr;
/**** unused as commented out
static const u16 evl_phy_value[] = {
0x8B56, 0x8B5F, 0x8B68, 0x8B71,
0x8B7A, 0x8A7B, 0x8A7E, 0x8A81,
0x8A84, 0x8A87
};
*/
// Copied from rtl8168_hw_start()
void RealtekR1000::RTL8168HwStart()
{
switch (mcfg) {
case MCFG_8168B_1:
case MCFG_8168B_2:
case MCFG_8168B_3:
case MCFG_8168C_1:
case MCFG_8168C_2:
case MCFG_8168C_3:
case MCFG_8168CP_1:
case MCFG_8168CP_2:
case MCFG_8168D_1:
case MCFG_8168D_2:
case MCFG_8168DP_1:
case MCFG_8168DP_2:
case MCFG_8168DP_3:
case MCFG_8168E_1:
case MCFG_8168E_2:
break;
default:
WriteMMIO32(RxConfig, RxCfg_128_int_en | (RX_DMA_BURST << RxCfgDMAShift));
break;
}
RTL8168NicReset();
WriteMMIO8(Cfg9346, Cfg9346_Unlock);
WriteMMIO8(ETThReg, ETTh);
cp_cmd |= PktCntrDisable | INTT_1;
WriteMMIO16(CPlusCmd, cp_cmd);
WriteMMIO16(IntrMitigate, 0xcf68); //was 5151 but linux 5f51 Mieze cf68
WriteMMIO8(Config5, ReadMMIO8(Config5) & ~BIT_7); //as in Linux
intr_mask = rtl8168_intr_mask;
//Work around for RxFIFO overflow
if (mcfg == MCFG_8168B_1)
{
intr_mask |= RxFIFOOver | PCSTimeout;
intr_mask &= ~RxDescUnavail;
}
WriteMMIO32(TxDescStartAddr, static_cast<UInt32>(txdesc_phy_dma_addr));
#if defined(__LP64__)
WriteMMIO32(TxDescStartAddr + 4, static_cast<UInt32>(txdesc_phy_dma_addr >> 32));
#endif
WriteMMIO32(RxDescStartAddr, static_cast<UInt32>(rxdesc_phy_dma_addr));
#if defined(__LP64__)
WriteMMIO32(RxDescStartAddr + 4, static_cast<UInt32>(rxdesc_phy_dma_addr >> 32));
#endif
// Set Rx Config register to ignore all for now
WriteMMIO32(RxConfig,
~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys) &
(rx_config_base | (ReadMMIO32(RxConfig) & rx_config_mask)));
/* Set DMA burst size and Interframe Gap Time */
if (mcfg == MCFG_8168B_1)
{
WriteMMIO32(TxConfig,
(TX_DMA_BURST_512 << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift));
}
else
{
WriteMMIO32(TxConfig,
(TX_DMA_BURST_unlimited << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift));
}
/* Clear the interrupt status register. */
WriteMMIO16(IntrStatus, 0xFFFF);
if (!rx_fifo_overflow)
{
/* Enable all known interrupts by setting the interrupt mask. */
WriteMMIO16(IntrMask, intr_mask);
}
// Do model-dependent initialization
switch (mcfg)
{
case MCFG_8168B_1:
case MCFG_8168B_2:
case MCFG_8168B_3:
RTL8168BHwStart2();
break;
case MCFG_8168C_1:
case MCFG_8168C_2:
case MCFG_8168C_3:
RTL8168CHwStart2();
break;
case MCFG_8168CP_1:
case MCFG_8168CP_2:
RTL8168CPHwStart2();
break;
case MCFG_8168D_1:
case MCFG_8168D_2:
RTL8168DHwStart2();
break;
case MCFG_8168DP_1:
case MCFG_8168DP_2:
case MCFG_8168DP_3:
RTL8168DPHwStart2();
break;
case MCFG_8168E_1:
case MCFG_8168E_2:
RTL8168EHwStart2();
break;
case MCFG_8168E_VL_1:
case MCFG_8168E_VL_2:
RTL8168EVLHwStart2();
break;
case MCFG_8168F_1:
case MCFG_8168F_2:
case MCFG_8411_1:
case CFG_METHOD_21:
case CFG_METHOD_22:
case CFG_METHOD_23:
case CFG_METHOD_24:
case CFG_METHOD_25:
case MCFG_8411B:
case CFG_METHOD_27:
RTL8168FHwStart2();
break;
#ifdef DEBUG
default:
DLog("RTL8168HwStart: bad mcfg %d", mcfg);
cp_cmd &= 0x2043;
WriteMMIO8(ETThReg, 0x0C);
/* tx checksum offload disable */
canOffload &= ~kChecksumIP;
/* rx checksum offload disable */
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
// rtl8168_set_rxbufsize(tp, dev);
break;
#endif
}
if ((mcfg == MCFG_8168B_1) ||
(mcfg == MCFG_8168B_2) ||
(mcfg == MCFG_8168B_3))
{
/* csum offload command for RTL8168B/8111B */
tx_tcp_csum_cmd = TxIPCS | TxTCPCS;
tx_udp_csum_cmd = TxIPCS | TxUDPCS;
tx_ip_csum_cmd = TxIPCS;
}
else
{
/* csum offload command for RTL8168C/8111C, RTL8168CP/8111CP, RTL8168D/8111D, RTL8168DP/8111DP */
tx_tcp_csum_cmd = TxIPCS_C | TxTCPCS_C;
tx_udp_csum_cmd = TxIPCS_C | TxUDPCS_C;
tx_ip_csum_cmd = TxIPCS_C;
}
WriteMMIO16(CPlusCmd, cp_cmd);
WriteMMIO8(ChipCmd, CmdTxEnb | CmdRxEnb);
// Set Rx Config register
// Default to accept broadcast & my address, no multicast, no promiscuous
u32 rx_mode = (rx_config_base |
AcceptBroadcast | AcceptMyPhys |
(ReadMMIO32(RxConfig) & rtl_chip_info[mcfg].RxConfigMask));
WriteMMIO32(RxConfig, rx_mode);
// Set RxMaxSize register - thanks to Mieze
WriteMMIO16(RxMaxSize, 2000);
WriteMMIO8(Cfg9346, Cfg9346_Lock);
RTL8168DSM(DSM_MAC_INIT);
u8 options1 = ReadMMIO8(Config3);
u8 options2 = ReadMMIO8(Config5);
u32 csi_tmp = ReadERI(0xDE, 4, ERIAR_ExGMAC);
switch (mcfg) {
case MCFG_8168E_VL_1:
case MCFG_8168E_VL_2:
case MCFG_8168F_1:
case MCFG_8168F_2:
case MCFG_8411_1:
case CFG_METHOD_21:
case CFG_METHOD_22:
case CFG_METHOD_23:
case CFG_METHOD_24:
case CFG_METHOD_25:
case MCFG_8411B:
case CFG_METHOD_27:
if ((options1 & LinkUp) || (csi_tmp & BIT_0) || (options2 & UWF) || (options2 & BWF) || (options2 & MWF))
wol_enabled = WOL_ENABLED;
else
wol_enabled = WOL_DISABLED;
break;
default:
if ((options1 & LinkUp) ||
(options1 & MagicPacket) ||
(options2 & UWF) ||
(options2 & BWF) ||
(options2 & MWF))
wol_enabled = WOL_ENABLED;
else
wol_enabled = WOL_DISABLED;
break;
}
IODelay(10);
return;
}
// taken from rtl8168_hw_start()
void RealtekR1000::RTL8168BHwStart2()
{
u8 device_control;
if (mcfg == MCFG_8168B_1)
{
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable | Macdbgo_sel));
if (curr_mtu_size > ETHERMTU)
{
device_control = pciDev->configRead8(0x69);
device_control &= ~0x70;
device_control |= 0x28;
pciDev->configWrite8(0x69, device_control);
}
else
{
device_control = pciDev->configRead8(0x69);
device_control &= ~0x70;
device_control |= 0x58;
pciDev->configWrite8(0x69, device_control);
}
}
else if (mcfg == MCFG_8168B_2)
{
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable | Macdbgo_sel));
if (curr_mtu_size > ETHERMTU)
{
device_control = pciDev->configRead8(0x69);
device_control &= ~0x70;
device_control |= 0x28;
pciDev->configWrite8(0x69, device_control);
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config4, ReadMMIO8(Config4) | (1 << 0));
}
else
{
device_control = pciDev->configRead8(0x69);
device_control &= ~0x70;
device_control |= 0x58;
pciDev->configWrite8(0x69, device_control);
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~(1 << 0));
}
}
else if (mcfg == MCFG_8168B_3)
{
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable | Macdbgo_sel));
if (curr_mtu_size > ETHERMTU)
{
device_control = pciDev->configRead8(0x69);
device_control &= ~0x70;
device_control |= 0x28;
pciDev->configWrite8(0x69, device_control);
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config4, ReadMMIO8(Config4) | (1 << 0));
}
else
{
device_control = pciDev->configRead8(0x69);
device_control &= ~0x70;
device_control |= 0x58;
pciDev->configWrite8(0x69, device_control);
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~(1 << 0));
}
}
return;
}
// taken from rtl8168_hw_start()
void RealtekR1000::RTL8168CHwStart2()
{
u8 device_control;
u16 ephy_data;
u32 csi_tmp;
if (mcfg == MCFG_8168C_1)
{
/*set PCI configuration space offset 0x70F to 0x27*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x27000000);
WriteMMIO8(DBG_reg, (0x0E << 4) | Fix_Nak_1 | Fix_Nak_2);
/*Set EPHY registers begin*/
/*Set EPHY register offset 0x02 bit 11 to 0 and bit 12 to 1*/
ephy_data = ReadEPHY16(0x02);
ephy_data &= ~(1 << 11);
ephy_data |= (1 << 12);
WriteEPHY16(0x02, ephy_data);
/*Set EPHY register offset 0x03 bit 1 to 1*/
ephy_data = ReadEPHY16(0x03);
ephy_data |= (1 << 1);
WriteEPHY16(0x03, ephy_data);
/*Set EPHY register offset 0x06 bit 7 to 0*/
ephy_data = ReadEPHY16(0x06);
ephy_data &= ~(1 << 7);
WriteEPHY16(0x06, ephy_data);
/*Set EPHY registers end*/
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
//disable clock request.
pciDev->configWrite8(0x81, 0x00);
WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable | Macdbgo_sel));
if (curr_mtu_size > ETHERMTU)
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) | Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x20
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x20;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload disable
canOffload &= ~kChecksumIP;
//rx checksum offload disable
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
else
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x50
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload enable
canOffload |= kChecksumIP;
//rx checksum offload enable
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
}
else if (mcfg == MCFG_8168C_2)
{
/*set PCI configuration space offset 0x70F to 0x27*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x27000000);
/******set EPHY registers for RTL8168CP begin******/
//Set EPHY register offset 0x01 bit 0 to 1.
ephy_data = ReadEPHY16(0x01);
ephy_data |= (1 << 0);
WriteEPHY16(0x01, ephy_data);
//Set EPHY register offset 0x03 bit 10 to 0, bit 9 to 1 and bit 5 to 1.
ephy_data = ReadEPHY16(0x03);
ephy_data &= ~(1 << 10);
ephy_data |= (1 << 9);
ephy_data |= (1 << 5);
WriteEPHY16(0x03, ephy_data);
/******set EPHY registers for RTL8168CP end******/
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
//disable clock request.
pciDev->configWrite8(0x81, 0x00);
WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable | Macdbgo_sel));
if (curr_mtu_size > ETHERMTU)
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) | Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x20
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x20;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload disable
canOffload &= ~kChecksumIP;
//rx checksum offload disable
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
else
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x50
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload enable
canOffload |= kChecksumIP;
//rx checksum offload enable
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
}
else if (mcfg == MCFG_8168C_3)
{
/*set PCI configuration space offset 0x70F to 0x27*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x27000000);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
//disable clock request.
pciDev->configWrite8(0x81, 0x00);
WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable | Macdbgo_sel));
if (curr_mtu_size > ETHERMTU)
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) | Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x20
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x20;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload disable
canOffload &= ~kChecksumIP;
//rx checksum offload disable
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
else
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x50
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload enable
canOffload |= kChecksumIP;
//rx checksum offload enable
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
}
return;
}
// taken from rtl8168_hw_start()
void RealtekR1000::RTL8168CPHwStart2()
{
u8 device_control;
u32 csi_tmp;
if (mcfg == MCFG_8168CP_1)
{
/*set PCI configuration space offset 0x70F to 0x27*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x27000000);
WriteERI(0x1EC, 1, 0x07, ERIAR_ASF);
//disable clock request.
pciDev->configWrite8(0x81, 0x00);
WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable | Macdbgo_sel));
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
if (curr_mtu_size > ETHERMTU)
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) | Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x20
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x20;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload disable
canOffload &= ~kChecksumIP;
//rx checksum offload disable
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
else
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x50
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload enable
canOffload |= kChecksumIP;
//rx checksum offload enable
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
}
else if (mcfg == MCFG_8168CP_2)
{
/*set PCI configuration space offset 0x70F to 0x27*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x27000000);
WriteERI(0x1EC, 1, 0x07, ERIAR_ASF);
//disable clock request.
pciDev->configWrite8(0x81, 0x00);
WriteMMIO16(CPlusCmd, ReadMMIO16(CPlusCmd) &
~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en |
Cxpl_dbg_sel | ASF | PktCntrDisable | Macdbgo_sel));
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Beacon_en);
WriteMMIO8(0xD1, 0x20);
if (curr_mtu_size > ETHERMTU)
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) | Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x20
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x20;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload disable
canOffload &= ~kChecksumIP;
//rx checksum offload disable
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
else
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~Jumbo_En1);
//Set PCI configuration space offset 0x79 to 0x50
/*Increase the Tx performance*/
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
//tx checksum offload enable
canOffload |= kChecksumIP;
//rx checksum offload enable
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
}
return;
}
// taken from rtl8168_hw_start()
void RealtekR1000::RTL8168DHwStart2()
{
u8 device_control;
u32 csi_tmp;
if (mcfg == MCFG_8168D_1)
{
/*set PCI configuration space offset 0x70F to 0x13*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x13000000);
/* disable clock request. */
pciDev->configWrite8(0x81, 0x00);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~BIT_4);
WriteMMIO8(DBG_reg, ReadMMIO8(DBG_reg) | BIT_7 | BIT_1);
if (curr_mtu_size > ETHERMTU)
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) | Jumbo_En1);
/* Set PCI configuration space offset 0x79 to 0x20 */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x20;
pciDev->configWrite8(0x79, device_control);
/* tx checksum offload disable */
canOffload &= ~kChecksumIP;
/* rx checksum offload disable */
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
else
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~Jumbo_En1);
/* Set PCI configuration space offset 0x79 to 0x50 */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
/* tx checksum offload enable */
canOffload |= kChecksumIP;
/* rx checksum offload enable */
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
/* set EPHY registers */
WriteEPHY16(0x01, 0x7C7D);
WriteEPHY16(0x02, 0x091F);
WriteEPHY16(0x06, 0xB271);
WriteEPHY16(0x07, 0xCE00);
}
else if (mcfg == MCFG_8168D_2)
{
/*set PCI configuration space offset 0x70F to 0x13*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x27000000);
WriteMMIO8(DBG_reg, ReadMMIO8(DBG_reg) | BIT_7 | BIT_1);
if (curr_mtu_size > ETHERMTU)
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) | Jumbo_En1);
/* Set PCI configuration space offset 0x79 to 0x20 */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x20;
pciDev->configWrite8(0x79, device_control);
/* tx checksum offload disable */
canOffload &= ~kChecksumIP;
/* rx checksum offload disable */
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
else
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~Jumbo_En1);
/* Set PCI configuration space offset 0x79 to 0x50 */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
/* tx checksum offload enable */
canOffload |= kChecksumIP;
/* rx checksum offload enable */
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
WriteMMIO8(Config1, 0xDF);
/* set EPHY registers */
WriteEPHY16(0x01, 0x6C7F);
WriteEPHY16(0x02, 0x011F);
WriteEPHY16(0x03, 0xC1B2);
WriteEPHY16(0x1A, 0x0546);
WriteEPHY16(0x1C, 0x80C4);
WriteEPHY16(0x1D, 0x78E4);
WriteEPHY16(0x0A, 0x8100);
/* disable clock request. */
pciDev->configWrite8(0x81, 0x00);
WriteMMIO8(0xF3, ReadMMIO8(0xF3) | (1 << 2));
}
return;
}
// taken from rtl8168_hw_start()
void RealtekR1000::RTL8168DPHwStart2()
{
u8 device_control;
u32 csi_tmp;
/*set PCI configuration space offset 0x70F to 0x37*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x37000000);
/* Set PCI configuration space offset 0x79 to 0x50 */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
if (curr_mtu_size > ETHERMTU)
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
/* tx checksum offload disable */
canOffload &= ~kChecksumIP;
/* rx checksum offload disable */
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
else
{
WriteMMIO8(ETThReg, ETTh);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
/* tx checksum offload enable */
canOffload |= kChecksumIP;
/* rx checksum offload enable */
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
WriteMMIO8(Config1, 0xDF);
return;
}
void RealtekR1000::RTL8168EHwStart2()
{
u8 device_control;
u32 csi_tmp;
u16 ephy_data;
if (mcfg == MCFG_8168E_1 || mcfg == MCFG_8168E_2) {
// set_offset70F(tp, 0x27);
// set_offset79(tp, 0x50);
/*set PCI configuration space offset 0x70F to 0x37*/
/*When the register offset of PCI configuration space larger than 0xff, use CSI to access it.*/
csi_tmp = ReadCSI32(0x70c) & 0x00ffffff;
WriteCSI32(0x70c, csi_tmp | 0x27000000);
/* Set PCI configuration space offset 0x79 to 0x50 */
device_control = pciDev->configRead8(0x79);
device_control &= ~0x70;
device_control |= 0x50;
pciDev->configWrite8(0x79, device_control);
/* set EPHY registers */
ephy_data = ReadEPHY16(0x00) & ~0x0200;
ephy_data |= 0x0100;
WriteEPHY16(0x00, ephy_data);
ephy_data = ReadEPHY16(0x00);
ephy_data |= 0x0004;
WriteEPHY16(0x00, ephy_data);
ephy_data = ReadEPHY16(0x06) & ~0x0002;
ephy_data |= 0x0001;
WriteEPHY16(0x06, ephy_data);
ephy_data = ReadEPHY16(0x06);
ephy_data |= 0x0030;
WriteEPHY16(0x06, ephy_data);
ephy_data = ReadEPHY16(0x07);
ephy_data |= 0x2000;
WriteEPHY16(0x07, ephy_data);
ephy_data = ReadEPHY16(0x00);
ephy_data |= 0x0020;
WriteEPHY16(0x00, ephy_data);
ephy_data = ReadEPHY16(0x03) & ~0x5800;
ephy_data |= 0x2000;
WriteEPHY16(0x03, ephy_data);
ephy_data = ReadEPHY16(0x03);
ephy_data |= 0x0001;
WriteEPHY16(0x03, ephy_data);
ephy_data = ReadEPHY16(0x01) & ~0x0800;
ephy_data |= 0x1000;
WriteEPHY16(0x01, ephy_data);
ephy_data = ReadEPHY16(0x07);
ephy_data |= 0x4000;
WriteEPHY16(0x07, ephy_data);
ephy_data = ReadEPHY16(0x1E);
ephy_data |= 0x2000;
WriteEPHY16(0x1E, ephy_data);
WriteEPHY16(0x19, 0xFE6C);
ephy_data = ReadEPHY16(0x0A);
ephy_data |= 0x0040;
WriteEPHY16(0x0A, ephy_data);
cp_cmd &= 0x2063;
if (curr_mtu_size > ETHERMTU) {
WriteMMIO8(ETThReg, 0x24);
WriteMMIO8(Config3, ReadMMIO8(Config3) | Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) | 0x01);
/* tx checksum offload disable */
canOffload &= ~kChecksumIP;
/* rx checksum offload disable */
cp_cmd &= ~RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
} else {
WriteMMIO8(ETThReg, 0x0C);
WriteMMIO8(Config3, ReadMMIO8(Config3) & ~Jumbo_En0);
WriteMMIO8(Config4, ReadMMIO8(Config4) & ~0x01);
/* tx checksum offload enable */
canOffload |= kChecksumIP;
/* rx checksum offload enable */
cp_cmd |= RxChkSum;
WriteMMIO16(CPlusCmd, cp_cmd);
}
// rtl8168_set_rxbufsize(tp, dev);
// WriteMMIO8(0xF2, ReadMMIO8(0xF2) | BIT_0);
// WriteMMIO32(CounterAddrLow, ReadMMIO32(CounterAddrLow) | BIT_0);
WriteMMIO8(0xF3, ReadMMIO8(0xF3) | BIT_5);
WriteMMIO8(0xF3, ReadMMIO8(0xF3) & ~BIT_5);
// WriteMMIO8(0xD3, ReadMMIO8(0xD3) | BIT_3 | BIT_2);
WriteMMIO8(0xD0, ReadMMIO8(0xD0) | BIT_7 | BIT_6);
WriteMMIO8(0xD1, ReadMMIO8(0xD1) | BIT_2 | BIT_3);
WriteMMIO8(0xF1, ReadMMIO8(0xF1) | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_2 | BIT_1);