MIPS-Pipelined-Processor

Implementation of a 5-stage pipelined multicycle processor that uses MIPS architecture in verilog

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Imm_gen.v		Imm_gen.v
PC_adder_4.v		PC_adder_4.v
PC_value.v		PC_value.v
README.md		README.md
SCDataPath.v		SCDataPath.v
alu32.v		alu32.v
alu_control.v		alu_control.v
data_mem.v		data_mem.v
ex_mem.v		ex_mem.v
forwarding_mux.v		forwarding_mux.v
forwarding_unit.v		forwarding_unit.v
id_ex.v		id_ex.v
if_id.v		if_id.v
instruction_mem.v		instruction_mem.v
main_control.v		main_control.v
mem_wb.v		mem_wb.v
mux2by1.v		mux2by1.v
mux2by1_5bit.v		mux2by1_5bit.v
pc_4_adder.v		pc_4_adder.v
pc_adder.v		pc_adder.v
pc_mux.v		pc_mux.v
regfile.v		regfile.v
sign_extender.v		sign_extender.v
stalling_unit.v		stalling_unit.v

Provide feedback