From 895b4203f3fa749008c0786d054ba1d09e654e2f Mon Sep 17 00:00:00 2001 From: Vin Huang Date: Fri, 22 Nov 2024 12:00:46 +0000 Subject: [PATCH] Fix the packBIdx when HasEccHalf is ture but HasWMMA_V1 is false and scheduleIterAlg = 3 --- tensilelite/Tensile/KernelWriter.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tensilelite/Tensile/KernelWriter.py b/tensilelite/Tensile/KernelWriter.py index 1e8fe1767..4fc6f9099 100644 --- a/tensilelite/Tensile/KernelWriter.py +++ b/tensilelite/Tensile/KernelWriter.py @@ -1329,7 +1329,7 @@ def hasAnyDependency(lr: DSLoadInstruction, insts: List[Instruction]): packBIdx = packBIdx if tPB["bpe"] < 4 and (not kernel["UnrollMajorLDSB"] or kernel["ConvertAfterDS"]) else 0 else: packAIdx = packAIdx if tPA["localReadInstruction"].blockWidth == 0.25 else 0 - packBIdx = packAIdx if tPB["localReadInstruction"].blockWidth == 0.25 else 0 + packBIdx = packBIdx if tPB["localReadInstruction"].blockWidth == 0.25 else 0 numPack = (packAIdx + packBIdx) if kernel["ProblemType"]["Sparse"] and not kernel["DirectToVgprSparseMetadata"]: packMIdx = packMIdx if not kernel["UnrollMajorLDSMetadata"] else 0