ADMS does not set the "output" element of variables per Verilog-A standard

[tvrusso]

The Verilog-A standard (http://www.accellera.org/images/downloads/standards/v-ams/VAMS-LRM-2-4.pdf, section 3.2.1) states that module-scoped variables that have "desc" and/or "units" attributes should be considered "output variables". Output variables would typically be used for .OP output and other purposes.

ADMS does NOT set the "output" field of the variableprototype at all, even though the commentary in the adms.xml file indicates that this is what it should mean.

For Xyce, we're looking into how to add capability to our back-end to generate appropriate code to provide access to such variables from a netlist. Having this output field set right would have helped.

For the time being, we're working around it by having a little preprocessing template that sets the "output" flag ourselves. This is it:

<admst:template match="markOutputVariables">
<admst:for-each select="variable[input!='yes' and (exists(attribute[name='desc']) or exists(attribute[name='units'])) and module/name=block/name]">
<admst:value-to select="output" string="yes"/>
</admst:for-each>
</admst:template>

One would simply apply this template at the top of a back-end to get all the output marking right.
<admst:apply-templates select="/module" match="markOutputVariables"/>

It would be good if adms.implicit.xml did something like this already.