From 2becec9d75e3f2cfc6e4c2e872fbe2ed3afd8012 Mon Sep 17 00:00:00 2001 From: Chen Xi <48302201+Ivyfeather@users.noreply.github.com> Date: Wed, 20 Mar 2024 15:38:46 +0800 Subject: [PATCH] Update misc fixes to kunminghu branch (#170) * prefetch: fix tp-meta-req way width (#160) * Directory:fix perfCounter bug, match resp_bits with right valid and replacerInfo (#161) * chore: replace deprecated APIs (#164) * Update the clock gating primitive for VCS (#169) --------- Co-authored-by: Easton Man Co-authored-by: CYYYC13 <75767324+ruiszhang@users.noreply.github.com> Co-authored-by: Tang Haojin --- Utility | 2 +- rocket-chip | 2 +- src/main/resources/STD_CLKGT_func.v | 7 ++++ src/main/scala/huancun/Common.scala | 2 +- src/main/scala/huancun/inclusive/MSHR.scala | 6 ++-- .../huancun/noninclusive/Directory.scala | 32 +++++++++---------- .../scala/huancun/noninclusive/MSHR.scala | 10 +++--- 7 files changed, 34 insertions(+), 27 deletions(-) diff --git a/Utility b/Utility index 575aff86..1b7acf09 160000 --- a/Utility +++ b/Utility @@ -1 +1 @@ -Subproject commit 575aff86cc7463193671542e6adad565c2437c6e +Subproject commit 1b7acf0998ddf175527aa0609788c3fea1262b1f diff --git a/rocket-chip b/rocket-chip index 16b7bcb0..175dfe09 160000 --- a/rocket-chip +++ b/rocket-chip @@ -1 +1 @@ -Subproject commit 16b7bcb013350e49c9c11d80e17dcff842fccfd6 +Subproject commit 175dfe096e3b7c630f93ef328df1cf0b2ed55de1 diff --git a/src/main/resources/STD_CLKGT_func.v b/src/main/resources/STD_CLKGT_func.v index 271012df..922f6cff 100644 --- a/src/main/resources/STD_CLKGT_func.v +++ b/src/main/resources/STD_CLKGT_func.v @@ -10,6 +10,12 @@ module STD_CLKGT_func ( assign clk_en = E | TE; +`ifdef VCS + always @(CK or clk_en) begin + if (CK == 1'b0) + clk_en_reg <= clk_en; + end +`else `ifdef VERILATOR_5 always @(CK or clk_en) begin if (CK == 1'b0) @@ -20,6 +26,7 @@ module STD_CLKGT_func ( begin clk_en_reg = clk_en; end +`endif `endif assign Q = CK & clk_en_reg; diff --git a/src/main/scala/huancun/Common.scala b/src/main/scala/huancun/Common.scala index 498f4926..d1aa19ca 100644 --- a/src/main/scala/huancun/Common.scala +++ b/src/main/scala/huancun/Common.scala @@ -241,7 +241,7 @@ class TPmetaReq extends Bundle { // FIXME: parameterize the hard code val hartid = UInt(4.W) // max 16 harts val set = UInt(32.W) - val way = UInt(8.W) + val way = UInt(4.W) val wmode = Bool() val rawData = Vec(16, UInt((36-6).W)) } diff --git a/src/main/scala/huancun/inclusive/MSHR.scala b/src/main/scala/huancun/inclusive/MSHR.scala index df4ac155..eec60539 100644 --- a/src/main/scala/huancun/inclusive/MSHR.scala +++ b/src/main/scala/huancun/inclusive/MSHR.scala @@ -109,7 +109,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup( meta.state, - BRANCH, + BRANCH)( Seq( INVALID -> BRANCH, BRANCH -> BRANCH, @@ -392,7 +392,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr req.fromB, MuxLookup( Cat(meta.state, probe_next_state), - NtoN, + NtoN)( Seq( // TODO: optimize this Cat(TRUNK, TRUNK) -> TtoT, Cat(TIP, TIP) -> TtoT, @@ -428,7 +428,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, DirWrite, TagWr Mux( !req_acquire, req.param, - MuxLookup(req.param, req.param, Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT)) + MuxLookup(req.param, req.param)(Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT)) ) od.size := req.size diff --git a/src/main/scala/huancun/noninclusive/Directory.scala b/src/main/scala/huancun/noninclusive/Directory.scala index 34505911..08dae6cc 100644 --- a/src/main/scala/huancun/noninclusive/Directory.scala +++ b/src/main/scala/huancun/noninclusive/Directory.scala @@ -317,33 +317,33 @@ class Directory(implicit p: Parameters) assert(dirReadPorts == 1) val req_r = RegEnable(req.bits, req.fire) XSPerfAccumulate(cacheParams, "selfdir_A_req", req_r.replacerInfo.channel(0) && resp.valid) - XSPerfAccumulate(cacheParams, "selfdir_A_hit", req_r.replacerInfo.channel(0) && resp.valid && resp.bits.self.hit) + XSPerfAccumulate(cacheParams, "selfdir_A_hit", RegNext(req_r.replacerInfo.channel(0) && resp.valid) && resp.bits.self.hit) XSPerfAccumulate(cacheParams, "selfdir_B_req", req_r.replacerInfo.channel(1) && resp.valid) - XSPerfAccumulate(cacheParams, "selfdir_B_hit", req_r.replacerInfo.channel(1) && resp.valid && resp.bits.self.hit) + XSPerfAccumulate(cacheParams, "selfdir_B_hit", RegNext(req_r.replacerInfo.channel(1) && resp.valid) && resp.bits.self.hit) XSPerfAccumulate(cacheParams, "selfdir_C_req", req_r.replacerInfo.channel(2) && resp.valid) - XSPerfAccumulate(cacheParams, "selfdir_C_hit", req_r.replacerInfo.channel(2) && resp.valid && resp.bits.self.hit) + XSPerfAccumulate(cacheParams, "selfdir_C_hit", RegNext(req_r.replacerInfo.channel(2) && resp.valid) && resp.bits.self.hit) - XSPerfAccumulate(cacheParams, "selfdir_dirty", resp.valid && resp.bits.self.dirty) - XSPerfAccumulate(cacheParams, "selfdir_TIP", resp.valid && resp.bits.self.state === TIP) - XSPerfAccumulate(cacheParams, "selfdir_BRANCH", resp.valid && resp.bits.self.state === BRANCH) - XSPerfAccumulate(cacheParams, "selfdir_TRUNK", resp.valid && resp.bits.self.state === TRUNK) - XSPerfAccumulate(cacheParams, "selfdir_INVALID", resp.valid && resp.bits.self.state === INVALID) + XSPerfAccumulate(cacheParams, "selfdir_dirty", RegNext(resp.valid) && resp.bits.self.dirty) + XSPerfAccumulate(cacheParams, "selfdir_TIP", RegNext(resp.valid) && resp.bits.self.state === TIP) + XSPerfAccumulate(cacheParams, "selfdir_BRANCH", RegNext(resp.valid) && resp.bits.self.state === BRANCH) + XSPerfAccumulate(cacheParams, "selfdir_TRUNK", RegNext(resp.valid) && resp.bits.self.state === TRUNK) + XSPerfAccumulate(cacheParams, "selfdir_INVALID", RegNext(resp.valid) && resp.bits.self.state === INVALID) //val perfinfo = IO(new Bundle(){ // val perfEvents = Output(new PerfEventsBundle(numPCntHcDir)) //}) val perfinfo = IO(Output(Vec(numPCntHcDir, (UInt(6.W))))) val perfEvents = Seq( ("selfdir_A_req ", req_r.replacerInfo.channel(0) && resp.valid ), - ("selfdir_A_hit ", req_r.replacerInfo.channel(0) && resp.valid && resp.bits.self.hit), + ("selfdir_A_hit ", RegNext(req_r.replacerInfo.channel(0) && resp.valid) && resp.bits.self.hit), ("selfdir_B_req ", req_r.replacerInfo.channel(1) && resp.valid ), - ("selfdir_B_hit ", req_r.replacerInfo.channel(1) && resp.valid && resp.bits.self.hit), + ("selfdir_B_hit ", RegNext(req_r.replacerInfo.channel(1) && resp.valid) && resp.bits.self.hit), ("selfdir_C_req ", req_r.replacerInfo.channel(2) && resp.valid ), - ("selfdir_C_hit ", req_r.replacerInfo.channel(2) && resp.valid && resp.bits.self.hit), - ("selfdir_dirty ", resp.valid && resp.bits.self.dirty ), - ("selfdir_TIP ", resp.valid && resp.bits.self.state === TIP ), - ("selfdir_BRANCH ", resp.valid && resp.bits.self.state === BRANCH ), - ("selfdir_TRUNK ", resp.valid && resp.bits.self.state === TRUNK ), - ("selfdir_INVALID ", resp.valid && resp.bits.self.state === INVALID ), + ("selfdir_C_hit ", RegNext(req_r.replacerInfo.channel(2) && resp.valid) && resp.bits.self.hit), + ("selfdir_dirty ", RegNext(resp.valid) && resp.bits.self.dirty ), + ("selfdir_TIP ", RegNext(resp.valid) && resp.bits.self.state === TIP ), + ("selfdir_BRANCH ", RegNext(resp.valid) && resp.bits.self.state === BRANCH ), + ("selfdir_TRUNK ", RegNext(resp.valid) && resp.bits.self.state === TRUNK ), + ("selfdir_INVALID ", RegNext(resp.valid) && resp.bits.self.state === INVALID ), ) for (((perf_out,(perf_name,perf)),i) <- perfinfo.zip(perfEvents).zipWithIndex) { diff --git a/src/main/scala/huancun/noninclusive/MSHR.scala b/src/main/scala/huancun/noninclusive/MSHR.scala index c29455b4..5b8d3fae 100644 --- a/src/main/scala/huancun/noninclusive/MSHR.scala +++ b/src/main/scala/huancun/noninclusive/MSHR.scala @@ -139,7 +139,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S val replace_need_release = self_meta.state > replace_clients_perm || self_meta.dirty && isT(self_meta.state) val replace_param = MuxLookup( Cat(self_meta.state, replace_clients_perm), - TtoB, + TtoB)( Seq( Cat(BRANCH, INVALID) -> BtoN, Cat(BRANCH, BRANCH) -> BtoB, @@ -249,7 +249,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S new_self_meta.dirty := self_meta.hit && self_meta.dirty || req.dirty && isParamFromT(req.param) new_self_meta.state := MuxLookup( req.param, - self_meta.state, + self_meta.state)( Seq( TtoT -> TRUNK, TtoB -> TIP, @@ -345,7 +345,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S BRANCH ), ), - MuxLookup(self_meta.state, INVALID, Seq( + MuxLookup(self_meta.state, INVALID)(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, // if prefetch read && hit && self is Trunk @@ -1107,7 +1107,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S val probeack_param = MuxLookup( // TODO: optimize this Cat(highest_perm, probe_next_state(highest_perm, req.param)), - NtoN, + NtoN)( Seq( Cat(TRUNK, TRUNK) -> TtoT, Cat(TIP, TIP) -> TtoT, @@ -1159,7 +1159,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S Mux( !req_acquire, req.param, - MuxLookup(req.param, req.param, Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT)) + MuxLookup(req.param, req.param)(Seq(NtoB -> Mux(req_promoteT, toT, toB), BtoT -> toT, NtoT -> toT)) ) od.size := req.size od.way := meta_reg.self.way