Output for this circuit depends on order on NMOS side of NAND3.

[NickOveracker]

[NickOveracker]

Debug info for failed configuration:

[NickOveracker]

Debug info for successful configuration:

[NickOveracker]

Graph structure for the failed configuration:

VDD
GND
A+
B+
[D|C]+
D+
~[D|C]+
OUT+
A-
C-
D-
~[D|C]-
Y
[D|C]-
14
B-
C+
B+ A+
[D|C]+ A+
[D|C]+ B+
D- C-
~[D|C]- ~[D|C]+
Y OUT+
[D|C]- B-
D+ C+
A- GND
A- C-
A- D-
A- ~[D|C]-
A- Y
A- B-
C- GND
C- ~[D|C]-
C- Y
C- C+
D- C+
D- GND
D- ~[D|C]-
D- Y
~[D|C]- GND
~[D|C]- Y
Y GND
[D|C]- 14
[D|C]- A+
[D|C]- B+
[D|C]- [D|C]+
A+ 14
A+ VDD
A+ D+
A+ ~[D|C]+
A+ OUT+
B+ VDD
B+ D+
B+ ~[D|C]+
B+ OUT+
B+ 14
[D|C]+ 14
[D|C]+ VDD
[D|C]+ D+
[D|C]+ ~[D|C]+
[D|C]+ OUT+
D+ VDD
D+ ~[D|C]+
D+ OUT+
~[D|C]+ VDD
~[D|C]+ OUT+
OUT+ VDD

[NickOveracker]

The problem stemmed from the memoization technique used to avoid infinite recursion. When memoized nodes were encountered before being evaluated, they were processed as "false" (=inactive).

Fixing this required implementing a sort of trigger interrupt to finish evaluation of all nodes waiting on certain nodes to be processed.