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InterfaceBoard.syr
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
-->
Reading design: InterfaceBoard.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "InterfaceBoard.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "InterfaceBoard"
Output Format : NGC
Target Device : xc6slx45-3-fgg484
---- Source Options
Top Module Name : InterfaceBoard
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/home/nabav/Workspace/HexapodTestBench/UART_Transmitter.vhd" into library work
Parsing entity <UART_Transmitter>.
Parsing architecture <Behavioral> of entity <uart_transmitter>.
Parsing VHDL file "/home/nabav/Workspace/HexapodTestBench/UART_Receiver.vhd" into library work
Parsing entity <UART_Receiver>.
Parsing architecture <Behavioral> of entity <uart_receiver>.
Parsing VHDL file "/home/nabav/Workspace/HexapodTestBench/Interface_Board_Main_State_Machine.vhd" into library work
Parsing entity <Interface_Board_Main_State_Machine>.
Parsing architecture <Behavioral> of entity <interface_board_main_state_machine>.
Parsing VHDL file "/home/nabav/Workspace/HexapodTestBench/Frame_Transmitter.vhd" into library work
Parsing entity <Frame_Transmitter>.
Parsing architecture <Behavioral> of entity <frame_transmitter>.
Parsing VHDL file "/home/nabav/Workspace/HexapodTestBench/Frame_Receiver.vhd" into library work
Parsing entity <Frame_Receiver>.
Parsing architecture <Behavioral> of entity <frame_receiver>.
Parsing VHDL file "/home/nabav/Workspace/HexapodTestBench/Debounce.vhd" into library work
Parsing entity <Debounce>.
Parsing architecture <Behavioral> of entity <debounce>.
Parsing VHDL file "/home/nabav/Workspace/HexapodTestBench/InterfaceBoard.vhd" into library work
Parsing entity <InterfaceBoard>.
Parsing architecture <Behavioral> of entity <interfaceboard>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <InterfaceBoard> (architecture <Behavioral>) from library <work>.
Elaborating entity <Debounce> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <UART_Receiver> (architecture <Behavioral>) from library <work>.
Elaborating entity <UART_Transmitter> (architecture <Behavioral>) from library <work>.
Elaborating entity <Frame_Transmitter> (architecture <Behavioral>) from library <work>.
Elaborating entity <Debounce> (architecture <Behavioral>) with generics from library <work>.
Elaborating entity <Frame_Receiver> (architecture <Behavioral>) from library <work>.
Elaborating entity <Interface_Board_Main_State_Machine> (architecture <Behavioral>) from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <InterfaceBoard>.
Related source file is "/home/nabav/Workspace/HexapodTestBench/InterfaceBoard.vhd".
Summary:
no macro.
Unit <InterfaceBoard> synthesized.
Synthesizing Unit <Debounce_1>.
Related source file is "/home/nabav/Workspace/HexapodTestBench/Debounce.vhd".
depth = 8
Found 8-bit register for signal <debounce_sr>.
Found 1-bit register for signal <filtered>.
Summary:
inferred 9 D-type flip-flop(s).
Unit <Debounce_1> synthesized.
Synthesizing Unit <UART_Receiver>.
Related source file is "/home/nabav/Workspace/HexapodTestBench/UART_Receiver.vhd".
Found 1-bit register for signal <clk_rx>.
Found 1-bit register for signal <Clock_Synchronizer.RX_RS232_old>.
Found 10-bit register for signal <Serial_Rx_Shift_Register.sr>.
Found 8-bit register for signal <received_byte>.
Found 1-bit register for signal <received_byte_ready>.
Found 1-bit register for signal <Serial_Rx_Shift_Register.clk_rx_old>.
Found 8-bit register for signal <PC_Rx_Buffer<0>>.
Found 8-bit register for signal <PC_Rx_Buffer<1>>.
Found 8-bit register for signal <PC_Rx_Buffer<2>>.
Found 8-bit register for signal <PC_Rx_Buffer<3>>.
Found 8-bit register for signal <PC_Rx_Buffer<4>>.
Found 8-bit register for signal <PC_Rx_Buffer<5>>.
Found 8-bit register for signal <PC_Rx_Buffer<6>>.
Found 8-bit register for signal <PC_Rx_Buffer<7>>.
Found 8-bit register for signal <PC_Rx_Buffer<8>>.
Found 8-bit register for signal <PC_Rx_Buffer<9>>.
Found 8-bit register for signal <PC_Rx_Buffer<10>>.
Found 8-bit register for signal <PC_Rx_Buffer<11>>.
Found 8-bit register for signal <PC_Rx_Buffer<12>>.
Found 8-bit register for signal <PC_Rx_Buffer<13>>.
Found 8-bit register for signal <PC_Rx_Buffer<14>>.
Found 8-bit register for signal <PC_Rx_Buffer<15>>.
Found 8-bit register for signal <PC_Rx_Buffer<16>>.
Found 8-bit register for signal <PC_Rx_Buffer<17>>.
Found 8-bit register for signal <PC_Rx_Buffer<18>>.
Found 8-bit register for signal <PC_Rx_Buffer<19>>.
Found 8-bit register for signal <PC_Rx_Buffer<20>>.
Found 8-bit register for signal <PC_Rx_Buffer<21>>.
Found 8-bit register for signal <PC_Rx_Buffer<22>>.
Found 8-bit register for signal <PC_Rx_Buffer<23>>.
Found 8-bit register for signal <PC_Rx_Buffer<24>>.
Found 8-bit register for signal <PC_Rx_Buffer<25>>.
Found 1-bit register for signal <PC_Rx_Data_Ready>.
Found 3-bit register for signal <PC_Rx_Packet_Type>.
Found 3-bit register for signal <PC_Rx_Jack_Nember>.
Found 8-bit register for signal <PC_Rx_Parameter_Address>.
Found 16-bit register for signal <PC_Rx_Parameter_Value>.
Found 32-bit register for signal <PC_Rx_Jack1_Cyclic_Command>.
Found 32-bit register for signal <PC_Rx_Jack2_Cyclic_Command>.
Found 32-bit register for signal <PC_Rx_Jack3_Cyclic_Command>.
Found 32-bit register for signal <PC_Rx_Jack4_Cyclic_Command>.
Found 32-bit register for signal <PC_Rx_Jack5_Cyclic_Command>.
Found 32-bit register for signal <PC_Rx_Jack6_Cyclic_Command>.
Found 1-bit register for signal <Frame_Decoder.received_byte_ready_old>.
Found 9-bit register for signal <baudrate_prescaler_counter>.
Found 9-bit adder for signal <baudrate_prescaler_counter[8]_GND_8_o_add_1_OUT> created at line 45.
Found 8-bit adder for signal <n0293> created at line 116.
Found 8-bit adder for signal <n0296> created at line 116.
Found 8-bit adder for signal <n0299> created at line 116.
Found 8-bit adder for signal <n0302> created at line 116.
Found 8-bit adder for signal <n0305> created at line 116.
Found 8-bit adder for signal <n0308> created at line 116.
Found 8-bit adder for signal <n0311> created at line 116.
Found 8-bit adder for signal <n0314> created at line 116.
Found 8-bit adder for signal <n0317> created at line 116.
Found 8-bit adder for signal <n0320> created at line 116.
Found 8-bit adder for signal <n0323> created at line 116.
Found 8-bit adder for signal <n0326> created at line 116.
Found 8-bit adder for signal <n0329> created at line 116.
Found 8-bit adder for signal <n0332> created at line 116.
Found 8-bit adder for signal <n0335> created at line 116.
Found 8-bit adder for signal <n0338> created at line 116.
Found 8-bit adder for signal <n0341> created at line 116.
Found 8-bit adder for signal <n0344> created at line 116.
Found 8-bit adder for signal <n0347> created at line 116.
Found 8-bit adder for signal <n0350> created at line 116.
Found 8-bit adder for signal <n0353> created at line 116.
Found 8-bit adder for signal <n0356> created at line 116.
Found 8-bit adder for signal <n0359> created at line 116.
Found 8-bit adder for signal <n0362> created at line 116.
Found 8-bit adder for signal <checksum> created at line 116.
Found 8x1-bit Read Only RAM for signal <PC_Rx_Buffer[0][2]_GND_8_o_Mux_39_o>
Found 9-bit comparator lessequal for signal <n0002> created at line 42
Found 9-bit comparator lessequal for signal <baudrate_prescaler_counter[8]_GND_8_o_LessThan_4_o> created at line 47
Summary:
inferred 1 RAM(s).
inferred 26 Adder/Subtractor(s).
inferred 463 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <UART_Receiver> synthesized.
Synthesizing Unit <UART_Transmitter>.
Related source file is "/home/nabav/Workspace/HexapodTestBench/UART_Transmitter.vhd".
Found 1-bit register for signal <TX_RS232>.
Found 4-bit register for signal <bit_number>.
Found 5-bit register for signal <byte_number>.
Found 2-bit register for signal <state>.
Found 8-bit register for signal <PC_Tx_Buffer<0>>.
Found 8-bit register for signal <PC_Tx_Buffer<1>>.
Found 8-bit register for signal <PC_Tx_Buffer<2>>.
Found 8-bit register for signal <PC_Tx_Buffer<3>>.
Found 8-bit register for signal <PC_Tx_Buffer<4>>.
Found 8-bit register for signal <PC_Tx_Buffer<5>>.
Found 8-bit register for signal <PC_Tx_Buffer<6>>.
Found 8-bit register for signal <PC_Tx_Buffer<7>>.
Found 8-bit register for signal <PC_Tx_Buffer<8>>.
Found 8-bit register for signal <PC_Tx_Buffer<9>>.
Found 8-bit register for signal <PC_Tx_Buffer<10>>.
Found 8-bit register for signal <PC_Tx_Buffer<11>>.
Found 8-bit register for signal <PC_Tx_Buffer<12>>.
Found 8-bit register for signal <PC_Tx_Buffer<13>>.
Found 8-bit register for signal <PC_Tx_Buffer<14>>.
Found 8-bit register for signal <PC_Tx_Buffer<15>>.
Found 8-bit register for signal <PC_Tx_Buffer<16>>.
Found 8-bit register for signal <PC_Tx_Buffer<17>>.
Found 8-bit register for signal <PC_Tx_Buffer<18>>.
Found 8-bit register for signal <PC_Tx_Buffer<19>>.
Found 8-bit register for signal <PC_Tx_Buffer<20>>.
Found 8-bit register for signal <PC_Tx_Buffer<21>>.
Found 8-bit register for signal <PC_Tx_Buffer<22>>.
Found 8-bit register for signal <PC_Tx_Buffer<23>>.
Found 8-bit register for signal <PC_Tx_Buffer<24>>.
Found 1-bit register for signal <UART_Tx_FSM.PC_Response_Ready_old>.
Found 9-bit register for signal <baudrate_prescaler_counter>.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 13 |
| Inputs | 8 |
| Outputs | 2 |
| Clock | clk (rising_edge) |
| Power Up State | idle |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 9-bit adder for signal <baudrate_prescaler_counter[8]_GND_9_o_add_1_OUT> created at line 44.
Found 4-bit adder for signal <bit_number[3]_GND_9_o_add_38_OUT> created at line 107.
Found 5-bit adder for signal <byte_number[4]_GND_9_o_add_40_OUT> created at line 112.
Found 3-bit subtractor for signal <GND_9_o_GND_9_o_sub_35_OUT<2:0>> created at line 101.
Found 8-bit adder for signal <_n0428> created at line 31.
Found 8-bit adder for signal <_n0429> created at line 31.
Found 8-bit adder for signal <_n0430> created at line 31.
Found 8-bit adder for signal <_n0431> created at line 31.
Found 8-bit adder for signal <_n0432> created at line 31.
Found 8-bit adder for signal <_n0433> created at line 31.
Found 8-bit adder for signal <_n0434> created at line 31.
Found 8-bit adder for signal <_n0435> created at line 31.
Found 8-bit adder for signal <_n0436> created at line 31.
Found 8-bit adder for signal <_n0437> created at line 31.
Found 8-bit adder for signal <_n0438> created at line 31.
Found 8-bit adder for signal <_n0439> created at line 31.
Found 8-bit adder for signal <_n0440> created at line 31.
Found 8-bit adder for signal <_n0441> created at line 31.
Found 8-bit adder for signal <_n0442> created at line 31.
Found 8-bit adder for signal <_n0443> created at line 31.
Found 8-bit adder for signal <_n0444> created at line 31.
Found 8-bit adder for signal <_n0445> created at line 31.
Found 8-bit adder for signal <_n0446> created at line 31.
Found 8-bit adder for signal <_n0447> created at line 31.
Found 8-bit adder for signal <_n0448> created at line 31.
Found 8-bit adder for signal <_n0449> created at line 31.
Found 8-bit adder for signal <_n0450> created at line 31.
Found 8-bit adder for signal <_n0451> created at line 31.
Found 8-bit subtractor for signal <checksum> created at line 31.
Found 8-bit 26-to-1 multiplexer for signal <byte_number[4]_X_9_o_wide_mux_33_OUT> created at line 101.
Found 1-bit 8-to-1 multiplexer for signal <GND_9_o_byte_number[4]_Mux_35_o> created at line 101.
Found 9-bit comparator greater for signal <n0000> created at line 41
Found 4-bit comparator greater for signal <bit_number[3]_PWR_9_o_LessThan_38_o> created at line 106
Found 5-bit comparator greater for signal <byte_number[4]_PWR_9_o_LessThan_40_o> created at line 111
Summary:
inferred 29 Adder/Subtractor(s).
inferred 220 D-type flip-flop(s).
inferred 3 Comparator(s).
inferred 33 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <UART_Transmitter> synthesized.
Synthesizing Unit <Frame_Transmitter>.
Related source file is "/home/nabav/Workspace/HexapodTestBench/Frame_Transmitter.vhd".
Found 1-bit register for signal <TX_RS485>.
Found 1-bit register for signal <Tx_Busy>.
Found 6-bit register for signal <bit_number>.
Found 3-bit register for signal <bus_hold_counter>.
Found 3-bit register for signal <state>.
Found 1-bit register for signal <Tx_Buffer<39>>.
Found 1-bit register for signal <Tx_Buffer<38>>.
Found 1-bit register for signal <Tx_Buffer<37>>.
Found 1-bit register for signal <Tx_Buffer<36>>.
Found 1-bit register for signal <Tx_Buffer<35>>.
Found 1-bit register for signal <Tx_Buffer<34>>.
Found 1-bit register for signal <Tx_Buffer<33>>.
Found 1-bit register for signal <Tx_Buffer<32>>.
Found 1-bit register for signal <Tx_Buffer<31>>.
Found 1-bit register for signal <Tx_Buffer<30>>.
Found 1-bit register for signal <Tx_Buffer<29>>.
Found 1-bit register for signal <Tx_Buffer<28>>.
Found 1-bit register for signal <Tx_Buffer<27>>.
Found 1-bit register for signal <Tx_Buffer<26>>.
Found 1-bit register for signal <Tx_Buffer<25>>.
Found 1-bit register for signal <Tx_Buffer<24>>.
Found 1-bit register for signal <Tx_Buffer<23>>.
Found 1-bit register for signal <Tx_Buffer<22>>.
Found 1-bit register for signal <Tx_Buffer<21>>.
Found 1-bit register for signal <Tx_Buffer<20>>.
Found 1-bit register for signal <Tx_Buffer<19>>.
Found 1-bit register for signal <Tx_Buffer<18>>.
Found 1-bit register for signal <Tx_Buffer<17>>.
Found 1-bit register for signal <Tx_Buffer<16>>.
Found 1-bit register for signal <Tx_Buffer<15>>.
Found 1-bit register for signal <Tx_Buffer<14>>.
Found 1-bit register for signal <Tx_Buffer<13>>.
Found 1-bit register for signal <Tx_Buffer<12>>.
Found 1-bit register for signal <Tx_Buffer<11>>.
Found 1-bit register for signal <Tx_Buffer<10>>.
Found 1-bit register for signal <Tx_Buffer<9>>.
Found 1-bit register for signal <Tx_Buffer<8>>.
Found 1-bit register for signal <Frame_Tx_FSM.Tx_Start_old>.
Found 6-bit register for signal <baudrate_prescaler_counter>.
INFO:Xst:1799 - State hold_bus_idle is never reached in FSM <state>.
Found finite state machine <FSM_1> for signal <state>.
-----------------------------------------------------------------------
| States | 7 |
| Transitions | 12 |
| Inputs | 5 |
| Outputs | 4 |
| Clock | clk (rising_edge) |
| Power Up State | idle |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 6-bit adder for signal <baudrate_prescaler_counter[5]_GND_10_o_add_1_OUT> created at line 38.
Found 3-bit adder for signal <bus_hold_counter[2]_GND_10_o_add_17_OUT> created at line 81.
Found 6-bit subtractor for signal <GND_10_o_GND_10_o_sub_13_OUT<5:0>> created at line 72.
Found 8-bit adder for signal <_n0162> created at line 25.
Found 8-bit adder for signal <_n0163> created at line 25.
Found 8-bit adder for signal <_n0164> created at line 25.
Found 8-bit subtractor for signal <checksum> created at line 25.
Found 1-bit 40-to-1 multiplexer for signal <bit_number[5]_X_10_o_Mux_7_o> created at line 62.
Found 6-bit comparator greater for signal <n0000> created at line 35
Found 3-bit comparator greater for signal <bus_hold_counter[2]_PWR_12_o_LessThan_17_o> created at line 80
Summary:
inferred 7 Adder/Subtractor(s).
inferred 49 D-type flip-flop(s).
inferred 2 Comparator(s).
inferred 8 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <Frame_Transmitter> synthesized.
Synthesizing Unit <Debounce_2>.
Related source file is "/home/nabav/Workspace/HexapodTestBench/Debounce.vhd".
depth = 4
Found 4-bit register for signal <debounce_sr>.
Found 1-bit register for signal <filtered>.
Summary:
inferred 5 D-type flip-flop(s).
Unit <Debounce_2> synthesized.
Synthesizing Unit <Frame_Receiver>.
Related source file is "/home/nabav/Workspace/HexapodTestBench/Frame_Receiver.vhd".
Found 40-bit register for signal <Rx_Buffer>.
Found 1-bit register for signal <fresh_bit_received>.
Found 1-bit register for signal <Rx_Ready>.
Found 2-bit register for signal <Rx_Frame_Type>.
Found 3-bit register for signal <Rx_Jack_Nember>.
Found 8-bit register for signal <Rx_Parameter_Address>.
Found 16-bit register for signal <Rx_Parameter_Value>.
Found 1-bit register for signal <Receive_Shift_Register.RX_RS485_old>.
Found 7-bit register for signal <low_duration_counter>.
Found 7-bit adder for signal <low_duration_counter[6]_GND_12_o_add_1_OUT> created at line 38.
Found 8-bit adder for signal <n0077> created at line 62.
Found 8-bit adder for signal <n0080> created at line 62.
Found 8-bit adder for signal <n0083> created at line 62.
Found 8-bit adder for signal <checksum> created at line 62.
Found 7-bit comparator greater for signal <low_duration_counter[6]_PWR_15_o_LessThan_1_o> created at line 37
Found 7-bit comparator lessequal for signal <low_duration_counter[6]_GND_12_o_LessThan_26_o> created at line 60
Summary:
inferred 5 Adder/Subtractor(s).
inferred 79 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <Frame_Receiver> synthesized.
Synthesizing Unit <Interface_Board_Main_State_Machine>.
Related source file is "/home/nabav/Workspace/HexapodTestBench/Interface_Board_Main_State_Machine.vhd".
WARNING:Xst:647 - Input <Rx_Frame_Type> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 1-bit register for signal <Tx_Start>.
Found 1-bit register for signal <PC_Response_Ready>.
Found 5-bit register for signal <state>.
Found 2-bit register for signal <Tx_Frame_Type>.
Found 3-bit register for signal <Tx_Jack_Nember>.
Found 8-bit register for signal <Tx_Parameter_Address>.
Found 16-bit register for signal <Tx_Parameter_Value>.
Found 4-bit register for signal <sequence_number>.
Found 3-bit register for signal <PC_Tx_Packet_Type>.
Found 3-bit register for signal <PC_Tx_Jack_Nember>.
Found 8-bit register for signal <PC_Tx_Parameter_Address>.
Found 16-bit register for signal <PC_Tx_Parameter_Value>.
Found 16-bit register for signal <jack_feedbacks<0>>.
Found 16-bit register for signal <jack_feedbacks<1>>.
Found 16-bit register for signal <jack_feedbacks<2>>.
Found 16-bit register for signal <jack_feedbacks<3>>.
Found 16-bit register for signal <jack_feedbacks<4>>.
Found 16-bit register for signal <jack_feedbacks<5>>.
Found 16-bit register for signal <jack_feedbacks<6>>.
Found 16-bit register for signal <jack_feedbacks<7>>.
Found 16-bit register for signal <jack_feedbacks<8>>.
Found 16-bit register for signal <jack_feedbacks<9>>.
Found 16-bit register for signal <jack_feedbacks<10>>.
Found 16-bit register for signal <jack_feedbacks<11>>.
Found 1-bit register for signal <Main_FSM.PC_Rx_Data_Ready_old>.
Found 1-bit register for signal <Main_FSM.Tx_Busy_old>.
Found 1-bit register for signal <Main_FSM.Rx_Ready_old>.
Found 13-bit register for signal <Main_FSM.timeout_counter>.
Found finite state machine <FSM_2> for signal <state>.
-----------------------------------------------------------------------
| States | 21 |
| Transitions | 63 |
| Inputs | 17 |
| Outputs | 13 |
| Clock | clk (rising_edge) |
| Power Up State | idle |
| Encoding | auto |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 3-bit adder for signal <jack_of_the_sequence> created at line 70.
Found 13-bit adder for signal <Main_FSM.timeout_counter[12]_GND_13_o_add_91_OUT> created at line 242.
Found 4-bit adder for signal <sequence_number[3]_GND_13_o_add_144_OUT> created at line 268.
Found 16-bit 12-to-1 multiplexer for signal <sequence_number[3]_X_13_o_wide_mux_55_OUT> created at line 174.
Found 3-bit comparator equal for signal <PC_Rx_Jack_Nember[2]_Rx_Jack_Nember[2]_equal_40_o> created at line 154
Found 8-bit comparator equal for signal <PC_Rx_Parameter_Address[7]_Rx_Parameter_Address[7]_equal_41_o> created at line 154
Found 3-bit comparator equal for signal <jack_of_the_sequence[2]_Rx_Jack_Nember[2]_equal_99_o> created at line 256
Found 8-bit comparator equal for signal <read_address_of_the_sequence[7]_Rx_Parameter_Address[7]_equal_100_o> created at line 256
Found 4-bit comparator greater for signal <sequence_number[3]_PWR_16_o_LessThan_58_o> created at line 267
Summary:
inferred 3 Adder/Subtractor(s).
inferred 273 D-type flip-flop(s).
inferred 5 Comparator(s).
inferred 28 Multiplexer(s).
inferred 1 Finite State Machine(s).
Unit <Interface_Board_Main_State_Machine> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x1-bit single-port Read Only RAM : 1
# Adders/Subtractors : 70
13-bit adder : 1
3-bit adder : 2
3-bit subtractor : 1
4-bit adder : 2
5-bit adder : 1
6-bit adder : 1
6-bit subtractor : 1
7-bit adder : 1
8-bit adder : 56
8-bit subtractor : 2
9-bit adder : 2
# Registers : 115
1-bit register : 28
10-bit register : 1
13-bit register : 1
16-bit register : 17
2-bit register : 2
3-bit register : 7
32-bit register : 11
4-bit register : 3
40-bit register : 1
5-bit register : 1
6-bit register : 2
7-bit register : 1
8-bit register : 38
9-bit register : 2
# Comparators : 14
3-bit comparator equal : 2
3-bit comparator greater : 1
4-bit comparator greater : 2
5-bit comparator greater : 1
6-bit comparator greater : 1
7-bit comparator greater : 1
7-bit comparator lessequal : 1
8-bit comparator equal : 2
9-bit comparator greater : 1
9-bit comparator lessequal : 2
# Multiplexers : 69
1-bit 2-to-1 multiplexer : 6
1-bit 40-to-1 multiplexer : 1
1-bit 8-to-1 multiplexer : 1
13-bit 2-to-1 multiplexer : 11
16-bit 12-to-1 multiplexer : 1
16-bit 2-to-1 multiplexer : 4
2-bit 2-to-1 multiplexer : 1
3-bit 2-to-1 multiplexer : 6
4-bit 2-to-1 multiplexer : 5
5-bit 2-to-1 multiplexer : 2
6-bit 2-to-1 multiplexer : 2
8-bit 2-to-1 multiplexer : 28
8-bit 26-to-1 multiplexer : 1
# FSMs : 3
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
INFO:Xst:2261 - The FF/Latch <PC_Tx_Buffer_0_1> in Unit <PC_UART_Transmitter> is equivalent to the following 2 FFs/Latches, which will be removed : <PC_Tx_Buffer_0_6> <PC_Tx_Buffer_0_7>
INFO:Xst:2261 - The FF/Latch <PC_Tx_Buffer_0_3> in Unit <PC_UART_Transmitter> is equivalent to the following 2 FFs/Latches, which will be removed : <PC_Tx_Buffer_0_4> <PC_Tx_Buffer_0_5>
INFO:Xst:2261 - The FF/Latch <Tx_Buffer_39> in Unit <RS485_Frame_Transmitter> is equivalent to the following FF/Latch, which will be removed : <Tx_Buffer_37>
WARNING:Xst:1426 - The value init of the FF/Latch PC_Tx_Buffer_0_1 hinder the constant cleaning in the block PC_UART_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch Tx_Buffer_39 hinder the constant cleaning in the block RS485_Frame_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <PC_Tx_Buffer_0_3> has a constant value of 0 in block <PC_UART_Transmitter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <Serial_Rx_Shift_Register.sr_0> of sequential type is unconnected in block <PC_UART_Receiver>.
Synthesizing (advanced) Unit <Frame_Receiver>.
The following registers are absorbed into counter <low_duration_counter>: 1 register on signal <low_duration_counter>.
The following adders/subtractors are grouped into adder tree <Madd_checksum1> :
<Madd_n0077> in block <Frame_Receiver>, <Madd_n0080> in block <Frame_Receiver>, <Madd_n0083> in block <Frame_Receiver>, <Madd_checksum> in block <Frame_Receiver>.
Unit <Frame_Receiver> synthesized (advanced).
Synthesizing (advanced) Unit <Frame_Transmitter>.
The following registers are absorbed into counter <baudrate_prescaler_counter>: 1 register on signal <baudrate_prescaler_counter>.
The following adders/subtractors are grouped into adder tree <Madd__n01641> :
<Madd__n0162> in block <Frame_Transmitter>, <Madd__n0163> in block <Frame_Transmitter>.
Unit <Frame_Transmitter> synthesized (advanced).
Synthesizing (advanced) Unit <UART_Receiver>.
The following registers are absorbed into counter <baudrate_prescaler_counter>: 1 register on signal <baudrate_prescaler_counter>.
The following adders/subtractors are grouped into adder tree <Madd_checksum1> :
<Madd_n0293> in block <UART_Receiver>, <Madd_n0296> in block <UART_Receiver>, <Madd_n0299> in block <UART_Receiver>, <Madd_n0302> in block <UART_Receiver>, <Madd_n0305> in block <UART_Receiver>, <Madd_n0308> in block <UART_Receiver>, <Madd_n0311> in block <UART_Receiver>, <Madd_n0314> in block <UART_Receiver>, <Madd_n0317> in block <UART_Receiver>, <Madd_n0320> in block <UART_Receiver>, <Madd_n0323> in block <UART_Receiver>, <Madd_n0326> in block <UART_Receiver>, <Madd_n0329> in block <UART_Receiver>, <Madd_n0332> in block <UART_Receiver>, <Madd_n0335> in block <UART_Receiver>, <Madd_n0338> in block <UART_Receiver>, <Madd_n0341> in block <UART_Receiver>, <Madd_n0344> in block <UART_Receiver>, <Madd_n0347> in block <UART_Receiver>, <Madd_n0350> in block <UART_Receiver>, <Madd_n0353> in block <UART_Receiver>, <Madd_n0356> in block <UART_Receiver>, <Madd_n0359> in block <UART_Receiver>, <Madd_n0362> in block <UART_Receiver>, <Madd_checksum> in block <UART_Receiver>.
INFO:Xst:3231 - The small RAM <Mram_PC_Rx_Buffer[0][2]_GND_8_o_Mux_39_o> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
-----------------------------------------------------------------------
| ram_type | Distributed | |
-----------------------------------------------------------------------
| Port A |
| aspect ratio | 8-word x 1-bit | |
| weA | connected to signal <GND> | high |
| addrA | connected to signal <PC_Rx_Buffer<0><2:0>> | |
| diA | connected to signal <GND> | |
| doA | connected to internal node | |
-----------------------------------------------------------------------
Unit <UART_Receiver> synthesized (advanced).
Synthesizing (advanced) Unit <UART_Transmitter>.
The following registers are absorbed into counter <baudrate_prescaler_counter>: 1 register on signal <baudrate_prescaler_counter>.
The following adders/subtractors are grouped into adder tree <Msub_checksum1> :
<Madd__n0428> in block <UART_Transmitter>, <Madd__n0429> in block <UART_Transmitter>, <Madd__n0431> in block <UART_Transmitter>, <Madd__n0433> in block <UART_Transmitter>, <Madd__n0432> in block <UART_Transmitter>, <Madd__n0436> in block <UART_Transmitter>, <Madd__n0437> in block <UART_Transmitter>, <Madd__n0439> in block <UART_Transmitter>, <Madd__n0440> in block <UART_Transmitter>, <Madd__n0443> in block <UART_Transmitter>, <Madd__n0444> in block <UART_Transmitter>, <Madd__n0446> in block <UART_Transmitter>, <Madd__n0447> in block <UART_Transmitter>.
The following adders/subtractors are grouped into adder tree <Madd__n04511> :
<Madd__n0430> in block <UART_Transmitter>, <Madd__n0434> in block <UART_Transmitter>, <Madd__n0438> in block <UART_Transmitter>, <Madd__n0441> in block <UART_Transmitter>, <Madd__n0445> in block <UART_Transmitter>, <Madd__n0448> in block <UART_Transmitter>.
The following adders/subtractors are grouped into adder tree <Madd__n04501> :
<Madd__n0442> in block <UART_Transmitter>, <Madd__n0449> in block <UART_Transmitter>.
Unit <UART_Transmitter> synthesized (advanced).
WARNING:Xst:2677 - Node <Serial_Rx_Shift_Register.sr_0> of sequential type is unconnected in block <UART_Receiver>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# RAMs : 1
8x1-bit single-port distributed Read Only RAM : 1
# Adders/Subtractors : 9
13-bit adder : 1
3-bit adder : 2
3-bit subtractor : 1
4-bit adder : 2
5-bit adder : 1
6-bit subtractor : 1
8-bit subtractor : 1
# Adder Trees : 4
8-bit / 25-inputs adder tree : 1
8-bit / 26-inputs adder tree : 1
8-bit / 4-inputs adder tree : 1
8-bit / 5-inputs adder tree : 1
# Counters : 4
6-bit up counter : 1
7-bit up counter : 1
9-bit up counter : 2
# Registers : 1066
Flip-Flops : 1066
# Comparators : 14
3-bit comparator equal : 2
3-bit comparator greater : 1
4-bit comparator greater : 2
5-bit comparator greater : 1
6-bit comparator greater : 1
7-bit comparator greater : 1
7-bit comparator lessequal : 1
8-bit comparator equal : 2
9-bit comparator greater : 1
9-bit comparator lessequal : 2
# Multiplexers : 76
1-bit 2-to-1 multiplexer : 6
1-bit 26-to-1 multiplexer : 8
1-bit 40-to-1 multiplexer : 1
1-bit 8-to-1 multiplexer : 1
13-bit 2-to-1 multiplexer : 11
16-bit 12-to-1 multiplexer : 1
16-bit 2-to-1 multiplexer : 4
2-bit 2-to-1 multiplexer : 1
3-bit 2-to-1 multiplexer : 6
4-bit 2-to-1 multiplexer : 5
5-bit 2-to-1 multiplexer : 2
6-bit 2-to-1 multiplexer : 2
8-bit 2-to-1 multiplexer : 28
# FSMs : 3
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch PC_Tx_Buffer_0_1 hinder the constant cleaning in the block UART_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch PC_Tx_Buffer_0_6 hinder the constant cleaning in the block UART_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch PC_Tx_Buffer_0_7 hinder the constant cleaning in the block UART_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <PC_Tx_Buffer_0_3> has a constant value of 0 in block <UART_Transmitter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <PC_Tx_Buffer_0_4> has a constant value of 0 in block <UART_Transmitter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <PC_Tx_Buffer_0_5> has a constant value of 0 in block <UART_Transmitter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1426 - The value init of the FF/Latch Tx_Buffer_37 hinder the constant cleaning in the block Frame_Transmitter.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch Tx_Buffer_39 hinder the constant cleaning in the block Frame_Transmitter.
You should achieve better results by setting this init to 1.
INFO:Xst:2261 - The FF/Latch <PC_Tx_Buffer_0_1> in Unit <UART_Transmitter> is equivalent to the following 2 FFs/Latches, which will be removed : <PC_Tx_Buffer_0_6> <PC_Tx_Buffer_0_7>
INFO:Xst:2261 - The FF/Latch <Tx_Buffer_39> in Unit <Frame_Transmitter> is equivalent to the following FF/Latch, which will be removed : <Tx_Buffer_37>
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <PC_UART_Transmitter/FSM_0> on signal <state[1:2]> with user encoding.
------------------------------
State | Encoding
------------------------------
idle | 00
capture | 01
send_bit | 10
prepare_next_bit | 11
------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <RS485_Frame_Transmitter/FSM_1> on signal <state[1:3]> with user encoding.
------------------------------
State | Encoding
------------------------------
idle | 000
capture | 001
send_low | 010
send_bit | 011
send_high | 100
prepare_next_bit | 101
hold_bus_idle | unreached
------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <Main_FSM/FSM_2> on signal <state[1:5]> with user encoding.
--------------------------------------------------------
State | Encoding
--------------------------------------------------------
idle | 00000
decode | 00001
write_request | 00010
wait_for_write_request_transmitted | 00011
read_request | 00100
wait_for_read_request_transmitted | 00101
wait_for_read_done | 00110
read_response | 00111
cyclic_command | 01000
cyclic_write | 01001
wait_for_cyclic_write_transmitted | 01010
write_latch_commands | 01011
wait_for_write_latch_commands_transmitted | 01100
write_latch_feedbacks | 01101
wait_for_write_latch_feedbacks_transmitted | 01110
cyclic_feedback | 01111
cyclic_read | 10000
wait_for_cyclic_read_transmitted | 10001
wait_for_cyclic_read_done | 10010
check_end_of_read_sequence | 10011
cyclic_feedback_response | 10100
--------------------------------------------------------
WARNING:Xst:2677 - Node <bus_hold_counter_0> of sequential type is unconnected in block <Frame_Transmitter>.
WARNING:Xst:2677 - Node <bus_hold_counter_1> of sequential type is unconnected in block <Frame_Transmitter>.
WARNING:Xst:2677 - Node <bus_hold_counter_2> of sequential type is unconnected in block <Frame_Transmitter>.
WARNING:Xst:1710 - FF/Latch <PC_Tx_Packet_Type_1> (without init value) has a constant value of 1 in block <Interface_Board_Main_State_Machine>. This FF/Latch will be trimmed during the optimization process.
Optimizing unit <InterfaceBoard> ...
Optimizing unit <Debounce_1> ...
Optimizing unit <UART_Receiver> ...
Optimizing unit <UART_Transmitter> ...
Optimizing unit <Frame_Transmitter> ...
Optimizing unit <Frame_Receiver> ...
Optimizing unit <Interface_Board_Main_State_Machine> ...
WARNING:Xst:2677 - Node <RS485_Frame_Receiver/Rx_Frame_Type_1> of sequential type is unconnected in block <InterfaceBoard>.
WARNING:Xst:2677 - Node <RS485_Frame_Receiver/Rx_Frame_Type_0> of sequential type is unconnected in block <InterfaceBoard>.
WARNING:Xst:1293 - FF/Latch <RS485_Frame_Transmitter/baudrate_prescaler_counter_5> has a constant value of 0 in block <InterfaceBoard>. This FF/Latch will be trimmed during the optimization process.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block InterfaceBoard, actual ratio is 7.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 1094
Flip-Flops : 1094
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : InterfaceBoard.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1902
# GND : 1
# INV : 7
# LUT1 : 28
# LUT2 : 298
# LUT3 : 235
# LUT4 : 441
# LUT5 : 90
# LUT6 : 195
# MUXCY : 259
# MUXF7 : 51
# MUXF8 : 1
# VCC : 1
# XORCY : 295
# FlipFlops/Latches : 1094
# FD : 42
# FDE : 973
# FDR : 23
# FDRE : 47
# FDSE : 9
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 5
# IBUF : 2
# OBUF : 3
Device utilization summary:
---------------------------
Selected Device : 6slx45fgg484-3
Slice Logic Utilization:
Number of Slice Registers: 1094 out of 54576 2%
Number of Slice LUTs: 1294 out of 27288 4%
Number used as Logic: 1294 out of 27288 4%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1745
Number with an unused Flip Flop: 651 out of 1745 37%
Number with an unused LUT: 451 out of 1745 25%
Number of fully used LUT-FF pairs: 643 out of 1745 36%
Number of unique control sets: 41
IO Utilization:
Number of IOs: 6
Number of bonded IOBs: 6 out of 316 1%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 16 6%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 1094 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 10.499ns (Maximum Frequency: 95.248MHz)
Minimum input arrival time before clock: 1.903ns
Maximum output required time after clock: 4.067ns
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 10.499ns (frequency: 95.248MHz)
Total number of paths / destination ports: 23141717 / 2198
-------------------------------------------------------------------------
Delay: 10.499ns (Levels of Logic = 19)
Source: PC_UART_Receiver/PC_Rx_Buffer_2_0 (FF)
Destination: PC_UART_Receiver/PC_Rx_Packet_Type_2 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: PC_UART_Receiver/PC_Rx_Buffer_2_0 to PC_UART_Receiver/PC_Rx_Packet_Type_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 4 0.447 0.788 PC_UART_Receiver/PC_Rx_Buffer_2_0 (PC_UART_Receiver/PC_Rx_Buffer_2_0)
LUT2:I0->O 1 0.203 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd1_lut<0> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd1_lut<0>)
MUXCY:S->O 1 0.172 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd1_cy<0> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd1_cy<0>)
XORCY:CI->O 2 0.180 0.617 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd1_xor<1> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd_11)
LUT3:I2->O 1 0.205 0.580 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd25 (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd21)
LUT4:I3->O 1 0.205 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd2_lut<0>2 (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd2_lut<0>2)
MUXCY:S->O 1 0.172 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd2_cy<0>_1 (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd2_cy<0>2)
XORCY:CI->O 1 0.180 0.580 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd2_xor<0>_2 (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd_32)
LUT2:I1->O 1 0.205 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd5_lut<3> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd5_lut<3>)
MUXCY:S->O 1 0.172 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd5_cy<3> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd5_cy<3>)
XORCY:CI->O 2 0.180 0.617 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd5_xor<4> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd_45)
LUT3:I2->O 1 0.205 0.580 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd114 (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd114)
LUT4:I3->O 1 0.205 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd11_lut<0>5 (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd11_lut<0>5)
MUXCY:S->O 1 0.172 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd11_cy<0>_4 (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd11_cy<0>5)
XORCY:CI->O 1 0.180 0.580 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd11_xor<0>_5 (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd_611)
LUT2:I1->O 1 0.205 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd24_lut<6> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd24_lut<6>)
MUXCY:S->O 0 0.172 0.000 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd24_cy<6> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd24_cy<6>)
XORCY:CI->O 13 0.180 0.933 PC_UART_Receiver/ADDERTREE_INTERNAL_Madd24_xor<7> (PC_UART_Receiver/ADDERTREE_INTERNAL_Madd_724)
LUT5:I4->O 19 0.205 1.072 PC_UART_Receiver/PC_Rx_Buffer[0][7]_checksum[7]_AND_10_o3_rstpot (PC_UART_Receiver/PC_Rx_Buffer[0][7]_checksum[7]_AND_10_o3_rstpot)
LUT3:I2->O 1 0.205 0.000 PC_UART_Receiver/PC_Rx_Packet_Type_0_dpot1 (PC_UART_Receiver/PC_Rx_Packet_Type_0_dpot1)
FDE:D 0.102 PC_UART_Receiver/PC_Rx_Packet_Type_0
----------------------------------------
Total 10.499ns (4.152ns logic, 6.347ns route)
(39.5% logic, 60.5% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset: 1.903ns (Levels of Logic = 1)
Source: RX_RS485 (PAD)
Destination: RX_RS485_Debounce_Filter/debounce_sr_0 (FF)
Destination Clock: clk rising
Data Path: RX_RS485 to RX_RS485_Debounce_Filter/debounce_sr_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.222 0.579 RX_RS485_IBUF (RX_RS485_IBUF)
FD:D 0.102 RX_RS485_Debounce_Filter/debounce_sr_0
----------------------------------------
Total 1.903ns (1.324ns logic, 0.579ns route)
(69.6% logic, 30.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 3 / 3
-------------------------------------------------------------------------
Offset: 4.067ns (Levels of Logic = 1)
Source: RS485_Frame_Transmitter/Tx_Busy (FF)
Destination: DIR_RS485 (PAD)
Source Clock: clk rising
Data Path: RS485_Frame_Transmitter/Tx_Busy to DIR_RS485
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 18 0.447 1.049 RS485_Frame_Transmitter/Tx_Busy (RS485_Frame_Transmitter/Tx_Busy)
OBUF:I->O 2.571 DIR_RS485_OBUF (DIR_RS485)
----------------------------------------
Total 4.067ns (3.018ns logic, 1.049ns route)
(74.2% logic, 25.8% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 10.499| | | |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 8.56 secs
-->
Total memory usage is 401560 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 21 ( 0 filtered)
Number of infos : 7 ( 0 filtered)