-Wconversion Flag Does Not Warn on Ternary Expression

[hankhsu1996]

Describe the bug

When using a ternary expression in SystemVerilog code, slang does not issue a width mismatch warning when the -Wconversion flag is enabled. This behavior is inconsistent with direct assignments where the warning is correctly triggered.

To Reproduce

Run the following code with slang and the -Wconversion flag:

module test;
  initial begin
    static int a = 3;
    static int b = 5;
    static bit cond = 1;
    static longint result = 7;
    result = cond ? a : b;
  end
endmodule

When the assignment uses a ternary expression (result = cond ? a : b;), there is no warning, despite the width mismatch. However, when assigning directly without the ternary (result = a;), slang correctly triggers a warning.