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moduletest;
logic [7:0] k;
logic clk_i;
logic rst_ni;
always_ff @(posedge clk_i ornegedge rst_ni) beginif(~rst_ni) begin
k <= '{default: '0};
endelsebeginfor(int i =0; i <8; i +=1) beginif (i %2) k[i] <= i[0];
else k[i] <= i[1];
endendendendmodule
The i increment i += 1 incorrectly triggers the RegisterHasNoReset warning:
test.sv:10:31: warning: [SYNTHESIS-1] register 'i' has no value on reset, but the always_ff block has the reset signal on the sensitivity list. Consider moving the register to an always_ff that has no reset or set a value on reset
for(int i = 0; i < 8; i += 1) begin
The text was updated successfully, but these errors were encountered:
The
i
incrementi += 1
incorrectly triggers theRegisterHasNoReset
warning:The text was updated successfully, but these errors were encountered: