From 1fcb7211c6bb02c16d1f4df555706e7c0d24b7cb Mon Sep 17 00:00:00 2001 From: Artyom Goncharov Date: Thu, 27 Dec 2018 20:34:49 +0100 Subject: [PATCH] Use 4 byte spills and add issues numbers 4 byte spills is required for now, but there is a task to make it work any size spills(#52). --- include/llvm/CodeGen/TargetRegisterInfo.h | 4 +- .../M680x0/InstPrinter/M680x0InstPrinter.cpp | 2 +- lib/Target/M680x0/M680x0AsmPrinter.cpp | 6 +-- lib/Target/M680x0/M680x0CallingConv.h | 4 +- lib/Target/M680x0/M680x0CallingConv.td | 8 ++-- lib/Target/M680x0/M680x0ExpandPseudo.cpp | 4 +- lib/Target/M680x0/M680x0FrameLowering.cpp | 12 +++--- lib/Target/M680x0/M680x0FrameLowering.h | 2 +- lib/Target/M680x0/M680x0ISelDAGToDAG.cpp | 15 +++---- lib/Target/M680x0/M680x0ISelLowering.cpp | 39 +++++++++---------- lib/Target/M680x0/M680x0InstrArithmetic.td | 4 +- lib/Target/M680x0/M680x0InstrBuilder.h | 2 +- lib/Target/M680x0/M680x0InstrCompiler.td | 4 +- lib/Target/M680x0/M680x0InstrControl.td | 6 +-- lib/Target/M680x0/M680x0InstrData.td | 4 +- lib/Target/M680x0/M680x0InstrInfo.cpp | 21 +++++----- lib/Target/M680x0/M680x0InstrInfo.h | 2 +- lib/Target/M680x0/M680x0InstrInfo.td | 16 ++++---- lib/Target/M680x0/M680x0MCInstLower.cpp | 4 +- lib/Target/M680x0/M680x0RegisterInfo.cpp | 6 +-- lib/Target/M680x0/M680x0RegisterInfo.h | 5 +++ lib/Target/M680x0/M680x0RegisterInfo.td | 4 +- lib/Target/M680x0/M680x0Subtarget.cpp | 1 - lib/Target/M680x0/M680x0TargetMachine.cpp | 8 ++-- lib/Target/M680x0/M680x0TargetObjectFile.cpp | 2 +- .../M680x0/MCTargetDesc/M680x0AsmBackend.cpp | 8 ++-- .../M680x0/MCTargetDesc/M680x0BaseInfo.h | 3 +- .../MCTargetDesc/M680x0ELFObjectWriter.cpp | 2 +- .../MCTargetDesc/M680x0MCCodeEmitter.cpp | 2 +- 29 files changed, 101 insertions(+), 99 deletions(-) diff --git a/include/llvm/CodeGen/TargetRegisterInfo.h b/include/llvm/CodeGen/TargetRegisterInfo.h index 0fbff313765..2db3974395e 100644 --- a/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/include/llvm/CodeGen/TargetRegisterInfo.h @@ -317,13 +317,13 @@ class TargetRegisterInfo : public MCRegisterInfo { /// Return the size in bytes of the stack slot allocated to hold a spilled /// copy of a register from class RC. - unsigned getSpillSize(const TargetRegisterClass &RC) const { + virtual unsigned getSpillSize(const TargetRegisterClass &RC) const { return getRegClassInfo(RC).SpillSize / 8; } /// Return the minimum required alignment in bytes for a spill slot for /// a register of this class. - unsigned getSpillAlignment(const TargetRegisterClass &RC) const { + virtual unsigned getSpillAlignment(const TargetRegisterClass &RC) const { return getRegClassInfo(RC).SpillAlignment / 8; } diff --git a/lib/Target/M680x0/InstPrinter/M680x0InstPrinter.cpp b/lib/Target/M680x0/InstPrinter/M680x0InstPrinter.cpp index ecfec50e89e..86c439eb736 100644 --- a/lib/Target/M680x0/InstPrinter/M680x0InstPrinter.cpp +++ b/lib/Target/M680x0/InstPrinter/M680x0InstPrinter.cpp @@ -12,7 +12,7 @@ /// //===----------------------------------------------------------------------===// -// TODO finish printer, it does not conform to Motorola asm at all +// TODO #33 finish printer, it does not conform to Motorola asm at all #include "M680x0InstPrinter.h" diff --git a/lib/Target/M680x0/M680x0AsmPrinter.cpp b/lib/Target/M680x0/M680x0AsmPrinter.cpp index 0f635420fca..86a1f1238d3 100644 --- a/lib/Target/M680x0/M680x0AsmPrinter.cpp +++ b/lib/Target/M680x0/M680x0AsmPrinter.cpp @@ -13,7 +13,7 @@ /// //===----------------------------------------------------------------------===// -// TODO make it print Motorola asm +// TODO #33 make it print Motorola asm #include "M680x0AsmPrinter.h" @@ -81,11 +81,11 @@ void M680x0AsmPrinter::EmitInstruction(const MachineInstr *MI) { } void M680x0AsmPrinter::EmitFunctionBodyStart() { - // TODO + // TODO #33 } void M680x0AsmPrinter::EmitFunctionBodyEnd() { - // TODO + // TODO #33 } void M680x0AsmPrinter::EmitStartOfAsmFile(Module &M) { diff --git a/lib/Target/M680x0/M680x0CallingConv.h b/lib/Target/M680x0/M680x0CallingConv.h index 8c388a203cc..dece32c6f4d 100644 --- a/lib/Target/M680x0/M680x0CallingConv.h +++ b/lib/Target/M680x0/M680x0CallingConv.h @@ -35,7 +35,7 @@ class M680x0CCState : public CCState { }; /// NOTE this function is used to select registers for formal arguments and call -/// TODO Need to assigne all the pointers first +/// TODO #34 Need to assigne all the pointers first inline bool CC_M680x0_Any_AssignToReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, @@ -53,7 +53,7 @@ inline bool CC_M680x0_Any_AssignToReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT, M680x0::D1, }; - // SHIT rewrite this + // SHIT #34 rewrite this // NOTE This is probably wrong auto I = CCInfo.F.arg_begin(); int No = ValNo; diff --git a/lib/Target/M680x0/M680x0CallingConv.td b/lib/Target/M680x0/M680x0CallingConv.td index 9fbd8d2ea62..78549a74b2d 100644 --- a/lib/Target/M680x0/M680x0CallingConv.td +++ b/lib/Target/M680x0/M680x0CallingConv.td @@ -14,6 +14,8 @@ /// //===----------------------------------------------------------------------===// +// TODO #35 Verify C convention follows SysV M68K ABI + class CCIfSubtarget : CCIf" "(State.getMachineFunction().getSubtarget()).", F), A>; @@ -36,7 +38,7 @@ def RetCC_M680x0_C : CallingConv<[ ]>; /// M680x0 fastcc return convention. -/// TODO: +/// TODO #36 /// This convention allows to return upto 16 bytes in registers which can be /// split among 16 1-byte values or used for a single 16-byte value. def RetCC_M680x0_Fast : CallingConv<[ @@ -73,7 +75,7 @@ def CC_M680x0_Fast : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, /// The 'nest' parameter, if any, is passed in A1. - CCIfNest>, // FIXME is this correct? + CCIfNest>, // FIXME #2 is this correct? /// Since M680x0 uses %An for pointers and we want them be passed in regs /// too we have to use custom function. @@ -88,7 +90,7 @@ def CC_M680x0_C : CallingConv<[ CCIfType<[i1, i8, i16], CCPromoteToType>, /// The 'nest' parameter, if any, is passed in A1. - CCIfNest>, // FIXME is this correct? + CCIfNest>, // FIXME #2 is this correct? /// Use registers only if 'inreg' used and the call is not vararg CCIfNotVarArg>>>, diff --git a/lib/Target/M680x0/M680x0ExpandPseudo.cpp b/lib/Target/M680x0/M680x0ExpandPseudo.cpp index afb27fac168..882734b8e72 100644 --- a/lib/Target/M680x0/M680x0ExpandPseudo.cpp +++ b/lib/Target/M680x0/M680x0ExpandPseudo.cpp @@ -80,7 +80,7 @@ bool M680x0ExpandPseudo::ExpandMI(MachineBasicBlock &MBB, switch (Opcode) { default: return false; - /// TODO would be nice to infer all these parameters + /// TODO #37 would be nice to infer all these parameters case M680x0::MOVXd16d8: return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); @@ -257,7 +257,7 @@ bool M680x0ExpandPseudo::ExpandMI(MachineBasicBlock &MBB, // MIB = BuildMI(MBB, MBBI, DL, TII->get(M680x0::RTD)).addImm(StackAdj); } else { // Copy PC from stack to a free address(A0 or A1) register - // TODO check if it is really free + // TODO #38 check if it is really free BuildMI(MBB, MBBI, DL, TII->get(M680x0::MOV32aj), M680x0::A1) .addReg(M680x0::SP); diff --git a/lib/Target/M680x0/M680x0FrameLowering.cpp b/lib/Target/M680x0/M680x0FrameLowering.cpp index 7edc28c750b..29c3a5dd3a9 100644 --- a/lib/Target/M680x0/M680x0FrameLowering.cpp +++ b/lib/Target/M680x0/M680x0FrameLowering.cpp @@ -49,7 +49,7 @@ bool M680x0FrameLowering::hasFP(const MachineFunction &MF) const { TRI->needsStackRealignment(MF); } -// FIXME not only pushes.... +// FIXME #6 not only pushes.... bool M680x0FrameLowering::hasReservedCallFrame( const MachineFunction &MF) const { return !MF.getFrameInfo().hasVarSizedObjects() && @@ -115,7 +115,7 @@ int M680x0FrameLowering::getFrameIndexReference(const MachineFunction &MF, assert((-(Offset + StackSize)) % MFI.getObjectAlignment(FI) == 0); return Offset + StackSize; } - // FIXME: Support tail calls + // FIXME: #7 Support tail calls } else { if (!HasFP) return Offset + StackSize; @@ -424,7 +424,7 @@ int M680x0FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB, MBB.erase(PI); if (!doMergeWithPrevious) MBBI = NI; - // TODO check this + // TODO #40 check this // } else if (Opc == M680x0::LEA32p && // PI->getOperand(0).getReg() == StackPtr && // PI->getOperand(2).getReg() == StackPtr) { @@ -447,7 +447,7 @@ MachineInstrBuilder M680x0FrameLowering::BuildStackAdjustment( const DebugLoc &DL, int64_t Offset, bool InEpilogue) const { assert(Offset != 0 && "zero offset stack adjustment requested"); - // ??? in the original code for M680x0 Atom uses lea to adjust stack as an + // TODO #8 in the original code for M680x0 Atom uses lea to adjust stack as an // optimization, can be be this applied for M680x0? bool IsSub = Offset < 0; @@ -457,7 +457,7 @@ MachineInstrBuilder M680x0FrameLowering::BuildStackAdjustment( MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) .addReg(StackPtr) .addImm(AbsOffset); - // FIXME ATM there is no CCR in these inst + // FIXME #9 ATM there is no CCR in these inst MI->getOperand(3).setIsDead(); // The CCR implicit def is dead. return MI; } @@ -688,7 +688,7 @@ void M680x0FrameLowering::emitPrologue(MachineFunction &MF, emitCalleeSavedFrameMoves(MBB, MBBI, DL); } - // TODO interrupts... + // TODO #10 interrupts... // M680x0 Interrupt handling function cannot assume anything about the // direction flag (DF in CCR register). Clear this flag by creating "cld" // instruction in each prologue of interrupt handler function. diff --git a/lib/Target/M680x0/M680x0FrameLowering.h b/lib/Target/M680x0/M680x0FrameLowering.h index b1d238e7792..5e080ca6560 100644 --- a/lib/Target/M680x0/M680x0FrameLowering.h +++ b/lib/Target/M680x0/M680x0FrameLowering.h @@ -167,7 +167,7 @@ class M680x0FrameLowering : public TargetFrameLowering { void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int64_t NumBytes, bool InEpilogue) const; - /// TODO + /// TODO #39 /// Order the symbols in the local stack. /// We want to place the local stack objects in some sort of sensible order. /// The heuristic we use is to try and pack them according to static number diff --git a/lib/Target/M680x0/M680x0ISelDAGToDAG.cpp b/lib/Target/M680x0/M680x0ISelDAGToDAG.cpp index a053ad0383c..f9523bd23c5 100644 --- a/lib/Target/M680x0/M680x0ISelDAGToDAG.cpp +++ b/lib/Target/M680x0/M680x0ISelDAGToDAG.cpp @@ -43,7 +43,7 @@ namespace { /// isInt - Checks if an integer fits into the given bit width. /// non-templated version -/// FIXME move it somewhere +/// FIXME #11 move it somewhere inline bool isInt(unsigned N, int64_t x) { return N >= 64 || (-(INT64_C(1) << (N - 1)) <= x && x < (INT64_C(1) << (N - 1))); @@ -382,10 +382,7 @@ bool M680x0DAGToDAGISel::matchAddressBase(SDValue N, return true; } -/// TODO -/// Have no idea how it is node with M680x0 ATM -/// Here is some description: -/// https://lists.debian.org/debian-68k/2007/11/msg00071.html +/// TODO #41 Add TLS support bool M680x0DAGToDAGISel::matchLoadInAddress(LoadSDNode *N, M680x0ISelAddressMode &AM) { // SDValue Address = N->getOperand(1); @@ -426,7 +423,7 @@ bool M680x0DAGToDAGISel::matchAddressRecursively(SDValue N, // into it. Instead of handling this in every case, we handle it here. // PC relative addressing: %PC + 16-bit displacement! if (AM.isPCRelative()) { - // FIXME: JumpTable and ExternalSymbol address currently don't like + // FIXME #12 JumpTable and ExternalSymbol address currently don't like // displacements. It isn't very important, but this should be fixed for // consistency. // if (!(AM.ES || AM.MCSym) && AM.JT != -1) @@ -498,7 +495,7 @@ bool M680x0DAGToDAGISel::matchAddress(SDValue N, M680x0ISelAddressMode &AM) { // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has // a smaller encoding and avoids a scaled-index. - // TODO make sure it is an indexed mode + // TODO #13 make sure it is an indexed mode // if (AM.Scale == 2 && // AM.BaseType == M680x0ISelAddressMode::RegBase && // AM.BaseReg.getNode() == nullptr) { @@ -508,8 +505,8 @@ bool M680x0DAGToDAGISel::matchAddress(SDValue N, M680x0ISelAddressMode &AM) { // Post-processing: Convert foo to foo(%pc), even in non-PIC mode, // because it has a smaller encoding. - // TODO: Which other code models can use this? - // FIXME this must be done only if PC* modes are currently being matched + // TODO #13 Which other code models can use this? + // FIXME #13 this must be done only if PC* modes are currently being matched // if (TM.getCodeModel() == CodeModel::Small && // Subtarget->is64Bit() && // AM.Scale == 1 && diff --git a/lib/Target/M680x0/M680x0ISelLowering.cpp b/lib/Target/M680x0/M680x0ISelLowering.cpp index 8dbd3cd8119..c7868c5ac0d 100644 --- a/lib/Target/M680x0/M680x0ISelLowering.cpp +++ b/lib/Target/M680x0/M680x0ISelLowering.cpp @@ -104,7 +104,7 @@ M680x0TargetLowering::M680x0TargetLowering(const M680x0TargetMachine &TM, setOperationAction(OP, MVT::i8, Expand); setOperationAction( OP, MVT::i16, - Expand); // FIXME something wrong with custom lowering here + Expand); // FIXME #14 something wrong with custom lowering here setOperationAction(OP, MVT::i32, Expand); } @@ -227,7 +227,7 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, /// Return true if the calling convention is one that we can guarantee TCO for. static bool canGuaranteeTCO(CallingConv::ID CC) { return false; - // return CC == CallingConv::Fast; // TODO Since M68010 only + // return CC == CallingConv::Fast; // TODO #7 Since M68010 only } /// Return true if we might ever do TCO for calls with this calling convention. @@ -407,7 +407,7 @@ SDValue M680x0TargetLowering::LowerMemArgument( // Calculate SP offset of interrupt parameter, re-arrange the slot normally // taken by a return address. - // TODO interrupts + // TODO #10 interrupts // if (CallConv == CallingConv::M680x0_INTR) { // const M680x0Subtarget& Subtarget = // static_cast(DAG.getSubtarget()); @@ -419,7 +419,7 @@ SDValue M680x0TargetLowering::LowerMemArgument( // 1); // } - // FIXME: For now, all byval parameter objects are marked mutable. This can be + // FIXME #15 For now, all byval parameter objects are marked mutable. This can be // changed with more analysis. // In case of tail call optimization mark all arguments mutable. Since they // could be overwritten by lowering of arguments in case of a tail call. @@ -433,7 +433,7 @@ SDValue M680x0TargetLowering::LowerMemArgument( Bytes = 1; // Don't create zero-sized stack objects. int FI = MFI.CreateFixedObject(Bytes, Offset, isImmutable); // Adjust SP offset of interrupt parameter. - // TODO interrupts + // TODO #10 interrupts // if (CallConv == CallingConv::M680x0_INTR) { // MFI.setObjectOffset(FI, Offset); // } @@ -450,7 +450,7 @@ SDValue M680x0TargetLowering::LowerMemArgument( } // Adjust SP offset of interrupt parameter. - // TODO interrupts + // TODO #10 interrupts // if (CallConv == CallingConv::M680x0_INTR) { // MFI.setObjectOffset(FI, Offset); // } @@ -505,7 +505,7 @@ M680x0TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, M680x0MachineFunctionInfo *MFI = MF.getInfo(); // const M680x0RegisterInfo *TRI = Subtarget.getRegisterInfo(); - // TODO interrupts + // TODO #10 interrupts // if (CallConv == CallingConv::M680x0_INTR) // report_fatal_error("M680x0 interrupts may not be called directly"); @@ -513,10 +513,9 @@ M680x0TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (Attr.getValueAsString() == "true") isTailCall = false; - // FIXME check this + // FIXME #7 Add tailcalls support // if (Subtarget.isPICStyleGOT() && // !MF.getTarget().Options.GuaranteedTailCallOpt) { - // // TODO reqd more about this stuff // // If we are using a GOT, disable tail calls to external symbols with // // default visibility. Tail calling such a symbol requires using a GOT // // relocation, which forces early binding of the symbol. This breaks code @@ -572,7 +571,7 @@ M680x0TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); } - // TODO debug this: + // TODO #44 debug this: int FPDiff = 0; if (isTailCall && !IsSibcall && !IsMustTail) { // Lower arguments at fp - stackoffset + fpdiff. @@ -676,7 +675,7 @@ M680x0TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (!MemOpChains.empty()) Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); - // FIXME check this + // FIXME #16 Fix PIC style GOT // ??? The only time GOT is really needed is for Medium-PIC static data // ??? otherwise we are happy with pc-rel or static references // if (Subtarget.isPICStyleGOT()) { @@ -943,7 +942,7 @@ SDValue M680x0TargetLowering::LowerFormalArguments( MachineFrameInfo &MFI = MF.getFrameInfo(); - // TODO interrupts... + // TODO #10 interrupts... // if (CCID == CallingConv::M680x0_INTR) { // bool isLegal = Ins.size() == 1 || // (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) || @@ -1001,7 +1000,7 @@ SDValue M680x0TargetLowering::LowerFormalArguments( } // If value is passed via pointer - do a load. - // TODO debug how this really works + // TODO #45 debug how this really works // ??? May I remove this indirect shizzle? if (VA.getLocInfo() == CCValAssign::Indirect) ArgValue = @@ -1058,7 +1057,7 @@ SDValue M680x0TargetLowering::LowerFormalArguments( // Copy all forwards from physical to virtual registers. for (ForwardedRegister &F : Forwards) { - // FIXME: Can we use a less constrained schedule? + // FIXME #7 Can we use a less constrained schedule? SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT); F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT)); Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal); @@ -2282,7 +2281,7 @@ SDValue M680x0TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { bool IllegalFPCMov = false; if ((isM680x0LogicalCmp(Cmp) && !IllegalFPCMov) || - Opc == M680x0ISD::BT) { // FIXME + Opc == M680x0ISD::BT) { Cond = Cmp; addTest = false; } @@ -2475,7 +2474,7 @@ SDValue M680x0TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { SDValue Cmp = Cond.getOperand(1); unsigned Opc = Cmp.getOpcode(); - // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? + if (isM680x0LogicalCmp(Cmp) || Opc == M680x0ISD::BT) { Cond = Cmp; addTest = false; @@ -2958,7 +2957,7 @@ const MCExpr *M680x0TargetLowering::getPICJumpTableRelocBaseExpr( /// Callee pop is necessary to support tail calls. bool M680x0::isCalleePop(CallingConv::ID CallingConv, bool IsVarArg, bool GuaranteeTCO) { - // FIXME RTD is not available untill M68010 + // FIXME #7 RTD is not available untill M68010 return false; // // If GuaranteeTCO is true, we force some calls to be callee pop so that we // // can guarantee TCO. @@ -3309,7 +3308,7 @@ M680x0TargetLowering::EmitLoweredSelect(MachineInstr &MI, MachineBasicBlock * M680x0TargetLowering::EmitLoweredSegAlloca(MachineInstr &MI, MachineBasicBlock *BB) const { - // FIXME See Target TODO.md + // FIXME #17 See Target TODO.md llvm_unreachable("Cannot lower Segmented Stack Alloca with stack-split on"); } @@ -3450,7 +3449,7 @@ static SDValue combineCarryThroughADD(SDValue CCR) { // where Op could be BRCOND or CMOV. // static SDValue checkBoolTestSetCCCombine(SDValue Cmp, M680x0::CondCode &CC) { - // FIXME Read through, make sure it fits m68k + // FIXME #18 Read through, make sure it fits m68k // // This combine only operates on CMP-like nodes. // if (!(Cmp.getOpcode() == M680x0ISD::CMP || // (Cmp.getOpcode() == M680x0ISD::SUB && !Cmp->hasAnyUseOfValue(0)))) @@ -3634,7 +3633,7 @@ static SDValue combineSUBX(SDNode *N, SelectionDAG &DAG) { // Optimize RES, CCR = M680x0ISD::ADDX LHS, RHS, CCR static SDValue combineADDX(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI) { - // FIXME Read through, make sure it fits m68k + // FIXME #19 Read through, make sure it fits m68k // // If the LHS and RHS of the ADDX node are zero, then it can't overflow and // // the result is either zero or one (depending on the input carry bit). // // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. diff --git a/lib/Target/M680x0/M680x0InstrArithmetic.td b/lib/Target/M680x0/M680x0InstrArithmetic.td index ffa25a0ca6b..e01580ab3da 100644 --- a/lib/Target/M680x0/M680x0InstrArithmetic.td +++ b/lib/Target/M680x0/M680x0InstrArithmetic.td @@ -147,7 +147,7 @@ class MxBiArOp_FMR CMD, MxEncEA EA, MxEncExt EXT> : MxInst<(outs), (ins MEMOpd:$dst, TYPE.ROp:$opd), MN#"."#TYPE.Prefix#"\t$opd, $dst", - // FIXME These cannot consume CCR from MxAdd/MxSub which leads for + // FIXME #20 These cannot consume CCR from MxAdd/MxSub which leads for // MxAdd to survive the match and subsequent malmatch. /* [(store (NODE (TYPE.Load MEMPat:$dst), TYPE.VT:$opd), MEMPat:$dst)], */ [], @@ -160,7 +160,7 @@ class MxBiArOp_FMI CMD, MxEncEA MEMEA, MxEncExt MEMExt> : MxInst<(outs), (ins MEMOpd:$dst, TYPE.IOp:$opd), MN#"."#TYPE.Prefix#"\t$opd, $dst", - // FIXME Same as above + // FIXME #20 Same as above /* [(store (NODE (TYPE.Load MEMPat:$dst), TYPE.IPat:$opd), MEMPat:$dst)], */ [], MxArithImmEncoding, diff --git a/lib/Target/M680x0/M680x0InstrBuilder.h b/lib/Target/M680x0/M680x0InstrBuilder.h index 02be8d4bba0..c5870329d68 100644 --- a/lib/Target/M680x0/M680x0InstrBuilder.h +++ b/lib/Target/M680x0/M680x0InstrBuilder.h @@ -11,7 +11,7 @@ /// This file exposes functions that may be used with BuildMI from the /// MachineInstrBuilder.h file to handle M680x0'isms in a clean way. /// -/// TODO edit the following mem stuff +/// TODO #42 edit the following mem stuff /// The BuildMem function may be used with the BuildMI function to add entire /// memory references in a single, typed, function call. M680x0 memory /// references can be very complex expressions (described in the README), so diff --git a/lib/Target/M680x0/M680x0InstrCompiler.td b/lib/Target/M680x0/M680x0InstrCompiler.td index abf703d4eaa..f92635db8d9 100644 --- a/lib/Target/M680x0/M680x0InstrCompiler.td +++ b/lib/Target/M680x0/M680x0InstrCompiler.td @@ -90,13 +90,13 @@ def ADJCALLSTACKUP // Tail Call //===----------------------------------------------------------------------===// -// FIXME need to read more about TC in llvm +// FIXME #7 need to read more about TC in llvm // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they // can never use callee-saved registers. That is the purpose of the XR32_TC // register classes. -// FIXME: This is disabled for PIC mode because the global base +// FIXME #7 This is disabled for PIC mode because the global base // register which is part of the address mode may be assigned a // callee-saved register. def : Pat<(MxTCRet (load MxCP_ARII:$dst), imm:$adj), diff --git a/lib/Target/M680x0/M680x0InstrControl.td b/lib/Target/M680x0/M680x0InstrControl.td index ba9b29b9624..c0af67f878b 100644 --- a/lib/Target/M680x0/M680x0InstrControl.td +++ b/lib/Target/M680x0/M680x0InstrControl.td @@ -127,7 +127,7 @@ class MxJMP def JMP32j : MxJMP; -// FIXME M680x0 does not allow 16 bit indirect jumps use sext operands +// FIXME #21 M680x0 does not allow 16 bit indirect jumps use sext operands /* def JMP16r : MxInst<(outs), (ins M680x0_ARI16:$dst), */ /* "jmp\t$dst", */ /* [(brind AR16:$dst)]>; */ @@ -249,7 +249,7 @@ def TAILJMPj : MxPseudo<(outs), (ins MxARI32_TC:$dst)>; // Return //===----------------------------------------------------------------------===// -// TODO don't forget about LINK/UNLK +// TODO #43 don't forget about LINK/UNLK let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in { @@ -269,7 +269,7 @@ def RET : MxPseudo<(outs), (ins i32imm:$adj, variable_ops), "", // Use subx to materialize carry bit. let Uses = [CCR], Defs = [CCR], isPseudo = 1 in { -// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. +// FIXME #22 These are pseudo ops that should be replaced with Pat<> patterns. // However, Pat<> can't replicate the destination reg into the inputs of the // result. def SETCS_C8d : MxPseudo<(outs MxDRD8:$dst), (ins), "", diff --git a/lib/Target/M680x0/M680x0InstrData.td b/lib/Target/M680x0/M680x0InstrData.td index 982900c8fdf..dade596bb22 100644 --- a/lib/Target/M680x0/M680x0InstrData.td +++ b/lib/Target/M680x0/M680x0InstrData.td @@ -93,7 +93,7 @@ class MxMove_RM { -// FIXME tablegen defines implicitly created defs inside multiclass which +// NOTE tablegen defines implicitly created defs inside multiclass which // breaks some code like letting Pattern afterwards in _TC // REG <- (An)+ @@ -344,7 +344,7 @@ def : Pat<(store MxType32.BPat :$src, MxType32.BPat :$dst), def : Pat<(store MxType32.BPat :$src, MxType32.JPat :$dst), (MOV32ji MxType32.JOp :$dst, MxType32.IOp :$src)>; -// FIXME Tablegen needs to parse complex defm names inside the loop FFS +// FIXME #23 Tablegen needs to parse complex defm names inside the loop FFS // R <- M defm MOV8d : MMxMove_RM; diff --git a/lib/Target/M680x0/M680x0InstrInfo.cpp b/lib/Target/M680x0/M680x0InstrInfo.cpp index 5fcbe34537f..92350d7ce7e 100644 --- a/lib/Target/M680x0/M680x0InstrInfo.cpp +++ b/lib/Target/M680x0/M680x0InstrInfo.cpp @@ -167,7 +167,7 @@ void M680x0InstrInfo::AddZExt(MachineBasicBlock &MBB, And = M680x0::AND32di; } - // TODO use xor r,r to decrease size + // TODO #46 use xor r,r to decrease size BuildMI(MBB, I, DL, get(And), Reg).addReg(Reg).addImm(Mask); } @@ -328,7 +328,7 @@ bool M680x0InstrInfo::ExpandCCR(MachineInstrBuilder &MIB, bool isToCCR) const { if (isToCCR) { MIB->setDesc(get(M680x0::MOV16cd)); } else { - // FIXME M68010 or better is required + // FIXME #24 M68010 or better is required MIB->setDesc(get(M680x0::MOV16dc)); } @@ -558,36 +558,37 @@ bool M680x0InstrInfo::getStackSlotRange(const TargetRegisterClass *RC, void M680x0InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FI, + unsigned SrcReg, bool isKill, + int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { const MachineFunction &MF = *MBB.getParent(); - assert(MF.getFrameInfo().getObjectSize(FI) == 4 && + assert(MF.getFrameInfo().getObjectSize(FrameIndex) == 4 && "Stack slot too small for store"); unsigned Opc = getStoreRegOpcode(SrcReg, RC, TRI, Subtarget); DebugLoc DL = MBB.findDebugLoc(MI); - // (0,FI) <- $reg - addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FI) + // (0,FrameIndex) <- $reg + addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIndex) .addReg(SrcReg, getKillRegState(isKill)); } void M680x0InstrInfo::loadRegFromStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DstReg, - int FI, const TargetRegisterClass *RC, + int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { const MachineFunction &MF = *MBB.getParent(); - assert(MF.getFrameInfo().getObjectSize(FI) == 4 && + assert(MF.getFrameInfo().getObjectSize(FrameIndex) == 4 && "Stack slot too small for store"); unsigned Opc = getLoadRegOpcode(DstReg, RC, TRI, Subtarget); DebugLoc DL = MBB.findDebugLoc(MI); - addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DstReg), FI); + addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DstReg), FrameIndex); } /// Return a virtual register initialized with the the global base register /// value. Output instructions required to initialize the register in the /// function entry block, if necessary. /// -/// TODO: Eliminate this and move the code to M680x0MachineFunctionInfo. +/// TODOss #47 Eliminate this and move the code to M680x0MachineFunctionInfo. unsigned M680x0InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { M680x0MachineFunctionInfo *MxFI = MF->getInfo(); unsigned GlobalBaseReg = MxFI->getGlobalBaseReg(); diff --git a/lib/Target/M680x0/M680x0InstrInfo.h b/lib/Target/M680x0/M680x0InstrInfo.h index a0fb517e07e..2e2a6e2415f 100644 --- a/lib/Target/M680x0/M680x0InstrInfo.h +++ b/lib/Target/M680x0/M680x0InstrInfo.h @@ -128,7 +128,7 @@ static inline unsigned GetCondBranchFromCond(M680x0::CondCode CC) { } } -// FIXME would be nice tablegen to generate these predicates, mb tag based +// FIXME #25 would be nice tablegen to generate these predicates, mb tag based static inline unsigned IsCMP(unsigned Op) { switch (Op) { diff --git a/lib/Target/M680x0/M680x0InstrInfo.td b/lib/Target/M680x0/M680x0InstrInfo.td index c1a702651f7..2c39639643c 100644 --- a/lib/Target/M680x0/M680x0InstrInfo.td +++ b/lib/Target/M680x0/M680x0InstrInfo.td @@ -453,12 +453,12 @@ def MximmSExt8 : PatLeaf<(i8 imm)>; def MximmSExt16 : PatLeaf<(i16 imm)>; def MximmSExt32 : PatLeaf<(i32 imm)>; -// Used for Shifts and Rotations, since M680x0 immediates in these -// instructions are 1 <= i <= 8. -// Generally, if immediate is bigger than 8 it will be moved to a register -// and then an operation is performed. TODO you need to evaluate whether -// splitting one big shift(or rotate) into a few smaller is faster than doing -// a move, if so do custom lowering +// Used for Shifts and Rotations, since M680x0 immediates in these instructions +// are 1 <= i <= 8. Generally, if immediate is bigger than 8 it will be moved +// to a register and then an operation is performed. +// +// TODO #48 you need to evaluate whether splitting one big shift(or rotate) +// into a few smaller is faster than doing a move, if so do custom lowering def Mximm8_1to8 : ImmLeaf= 1 && Imm <= 8; }]>; def Mximm16_1to8 : ImmLeaf= 1 && Imm <= 8; }]>; def Mximm32_1to8 : ImmLeaf= 1 && Imm <= 8; }]>; @@ -513,8 +513,8 @@ def MxExtLoadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; // Type Fixtures are ValueType related information sets that usually go together //===----------------------------------------------------------------------===// -// TODO make it folded like MxType8.F.Op nad MxType8.F.Pat -// TODO move strings into META subclass +// TODO #49 make it folded like MxType8.F.Op nad MxType8.F.Pat +// TODO #49 move strings into META subclass class MxType EnableBasePointer( void M680x0RegisterInfo::anchor() {} M680x0RegisterInfo::M680x0RegisterInfo(const M680x0Subtarget &ST) - // FIXME not sure it this the correct value, it expects RA, but M680x0 + // FIXME x26 not sure it this the correct value, it expects RA, but M680x0 // passes IP anyway, how this works? : M680x0GenRegisterInfo(M680x0::A0, - // FIXME Tablegen these 0, 0, M680x0::PC), Subtarget(ST) { - // FIXME would be nice to have tablegen level name aliasing StackPtr = M680x0::SP; FramePtr = M680x0::A6; GlobalBasePtr = M680x0::A5; @@ -184,7 +182,7 @@ void M680x0RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int FIndex = (int)(Base.getIndex()); // unsigned Opc = MI.getOpcode(); - // FIXME there is no jmp from mem yet + // FIXME #7 there is no jmp from mem yet // bool AfterFPPop = Opc == M680x0::TAILJMPm || Opc == M680x0::TCRETURNmi; bool AfterFPPop = false; diff --git a/lib/Target/M680x0/M680x0RegisterInfo.h b/lib/Target/M680x0/M680x0RegisterInfo.h index 603332a2302..e630f840166 100644 --- a/lib/Target/M680x0/M680x0RegisterInfo.h +++ b/lib/Target/M680x0/M680x0RegisterInfo.h @@ -103,6 +103,11 @@ class M680x0RegisterInfo : public M680x0GenRegisterInfo { unsigned getGlobalBaseRegister() const { return GlobalBasePtr; } const TargetRegisterClass *intRegClass(unsigned Size) const; + + // FIXME #52 Actually implement any size spill and remove this override + unsigned getSpillSize(const TargetRegisterClass &RC) const override { + return 4; + } }; } // end namespace llvm diff --git a/lib/Target/M680x0/M680x0RegisterInfo.td b/lib/Target/M680x0/M680x0RegisterInfo.td index 4474973b746..22d9f6c0260 100644 --- a/lib/Target/M680x0/M680x0RegisterInfo.td +++ b/lib/Target/M680x0/M680x0RegisterInfo.td @@ -71,7 +71,7 @@ def SP : MxAliasReg<"sp", A7>; // def SSP : MxAliasReg<"ssp", A7>; // def ISP : MxAliasReg<"isp", A7>; -// TODO get rid of "pseudo" registers and use just MxReg variants and use +// TODO #50 get rid of "pseudo" registers and use just MxReg variants and use // HWEncoding's other 13 bits to encode type(and potentially other info) of // register. @@ -103,7 +103,7 @@ def AR32 : MxRegClass<[i32], 32, (add (sequence "A%u", 0, 6), SP)>; def AR32_NOSP : MxRegClass<[i32], 32, (add (sequence "A%u", 0, 6))>; // Index Register Classes -// FIXME try order D0, D1, A0, A1, ... +// FIXME #27 try order D0, D1, A0, A1, ... def XR16 : MxRegClass<[i16], 16, (add DR16, AR16)>; def XR32 : MxRegClass<[i32], 32, (add DR32, AR32)>; diff --git a/lib/Target/M680x0/M680x0Subtarget.cpp b/lib/Target/M680x0/M680x0Subtarget.cpp index 56c9dc19b2d..3f84015a4b1 100644 --- a/lib/Target/M680x0/M680x0Subtarget.cpp +++ b/lib/Target/M680x0/M680x0Subtarget.cpp @@ -37,7 +37,6 @@ using namespace llvm; extern bool FixGlobalBaseReg; /// Select the M680x0 CPU for the given triple and cpu name. -/// FIXME: Merge with the copy in M680x0MCTargetDesc.cpp static StringRef selectM680x0CPU(Triple TT, StringRef CPU) { if (CPU.empty() || CPU == "generic") { CPU = "M68000"; diff --git a/lib/Target/M680x0/M680x0TargetMachine.cpp b/lib/Target/M680x0/M680x0TargetMachine.cpp index 21f6e160644..1275061598e 100644 --- a/lib/Target/M680x0/M680x0TargetMachine.cpp +++ b/lib/Target/M680x0/M680x0TargetMachine.cpp @@ -33,7 +33,7 @@ extern "C" void LLVMInitializeM680x0Target() { namespace { -// FIXME this layout is true for M68000 original cpu, other variants will +// FIXME #28 this layout is true for M68000 original cpu, other variants will // affect DL computation std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options) { @@ -41,7 +41,7 @@ std::string computeDataLayout(const Triple &TT, StringRef CPU, // M680x0 is Big Endian Ret += "E"; - // FIXME how to wire it with the used object format? + // FIXME #28 how to wire it with the used object format? Ret += "-m:e"; // M680x0 pointers are always 32 bit wide even for 16 bit cpus @@ -50,7 +50,7 @@ std::string computeDataLayout(const Triple &TT, StringRef CPU, // M680x0 requires i8 to align on 2 byte boundry Ret += "-i8:8:8-i16:16:16-i32:32:32"; - // FIXME no floats at the moment + // FIXME #29 no floats at the moment // The registers can hold 8, 16, 32 bits Ret += "-n8:16:32"; @@ -78,7 +78,7 @@ CodeModel::Model getEffectiveCodeModel(Optional CM, } else if (CM == CodeModel::Large) { llvm_unreachable("Large code model is not supported"); } else if (CM == CodeModel::Kernel) { - // FIXME Kernel afaik is small cm plus some weird binding + // FIXME #31 Kernel afaik is small cm plus some weird binding llvm_unreachable("Kernel code model is not supported"); } return CM.getValue(); diff --git a/lib/Target/M680x0/M680x0TargetObjectFile.cpp b/lib/Target/M680x0/M680x0TargetObjectFile.cpp index ec4e1eff79b..ed72c97db3e 100644 --- a/lib/Target/M680x0/M680x0TargetObjectFile.cpp +++ b/lib/Target/M680x0/M680x0TargetObjectFile.cpp @@ -40,7 +40,7 @@ void M680x0ELFTargetObjectFile::Initialize(MCContext &Ctx, this->TM = &static_cast(TM); - // FIXME do i need them explicitly? + // FIXME #32 do i need them explicitly? SmallDataSection = getContext().getELFSection( ".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); diff --git a/lib/Target/M680x0/MCTargetDesc/M680x0AsmBackend.cpp b/lib/Target/M680x0/MCTargetDesc/M680x0AsmBackend.cpp index 2c27dea9123..4c52bbc7af6 100644 --- a/lib/Target/M680x0/MCTargetDesc/M680x0AsmBackend.cpp +++ b/lib/Target/M680x0/MCTargetDesc/M680x0AsmBackend.cpp @@ -139,7 +139,7 @@ static unsigned getRelaxedOpcodeArith(const MCInst &Inst) { switch (Op) { default: return Op; - // TODO there will be some relaxations for PCD and ARD mem for x20 + // NOTE there will be some relaxations for PCD and ARD mem for x20 } } @@ -162,7 +162,7 @@ bool M680x0AsmBackend::mayNeedRelaxation(const MCInst &Inst, // Check if the relaxable operand has an expression. For the current set of // relaxable instructions, the relaxable operand is always the last operand. - // FIXME will change for x20 mem + // NOTE will change for x20 mem unsigned RelaxableOp = Inst.getNumOperands() - 1; if (Inst.getOperand(RelaxableOp).isExpr()) return true; @@ -181,14 +181,14 @@ bool M680x0AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, // Relax if the value is too big for a (signed) i8. This means that byte-wide // instructions have to matched by default // - // NOTE + // NOTE // A branch to the immediately following instruction automatically // uses the 16-bit displacement format because the 8-bit // displacement field contains $00 (zero offset). return Value == 0 || int64_t(Value) != int64_t(int8_t(Value)); } -// FIXME: Can tblgen help at all here to verify there aren't other instructions +// NOTE Can tblgen help at all here to verify there aren't other instructions // we can relax? void M680x0AsmBackend::relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, diff --git a/lib/Target/M680x0/MCTargetDesc/M680x0BaseInfo.h b/lib/Target/M680x0/MCTargetDesc/M680x0BaseInfo.h index 3bd9b0c1037..e91aa267d3b 100644 --- a/lib/Target/M680x0/MCTargetDesc/M680x0BaseInfo.h +++ b/lib/Target/M680x0/MCTargetDesc/M680x0BaseInfo.h @@ -39,7 +39,8 @@ namespace M680x0 { enum { MemDisp = 0, MemBase = 1, - MemIndex = 2, // FIXME assumes Scale 1 for now + MemIndex = 2, // FIXME #3 assumes Scale 1 for now + MemOuter = 3 }; diff --git a/lib/Target/M680x0/MCTargetDesc/M680x0ELFObjectWriter.cpp b/lib/Target/M680x0/MCTargetDesc/M680x0ELFObjectWriter.cpp index 9364e3bfc3e..2d3290a87a9 100644 --- a/lib/Target/M680x0/MCTargetDesc/M680x0ELFObjectWriter.cpp +++ b/lib/Target/M680x0/MCTargetDesc/M680x0ELFObjectWriter.cpp @@ -62,7 +62,7 @@ getType(unsigned Kind, MCSymbolRefExpr::VariantKind &Modifier, bool &IsPCRel) { } } -// FIXME Should i split reloc types between pre x20 and the rest? +// FIXME #4 Should i split reloc types between pre x20 and the rest? unsigned M680x0ELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target, const MCFixup &Fixup, diff --git a/lib/Target/M680x0/MCTargetDesc/M680x0MCCodeEmitter.cpp b/lib/Target/M680x0/MCTargetDesc/M680x0MCCodeEmitter.cpp index c68d15d300e..a7ce9c55bed 100644 --- a/lib/Target/M680x0/MCTargetDesc/M680x0MCCodeEmitter.cpp +++ b/lib/Target/M680x0/MCTargetDesc/M680x0MCCodeEmitter.cpp @@ -186,7 +186,7 @@ static unsigned EmitConstant(uint64_t Val, unsigned Size, unsigned Pad, assert(uintDoesFit(Size, Val)); // Pad the instruction with zeros if any - // FIXME Actually emit zeros, since there might be trash in the buffer. + // FIXME #5 Actually emit zeros, since there might be trash in the buffer. Size += Pad; // Writing Value in host's endianness