Macro instruction expanded into multiple instructions

[ps-george]

Linked to earlier issue #28,

The assembler outputs these warnings:
Warning: macro instruction expanded into multiple instructions

It's because sometimes I'm not technically writing MIPS assembly - using instructions like sge, slt and mul.

The code all works as expected, and obviously there exist 1-to-1 mappings between the macro instructions and their expanded forms, so it's pretty trivial if not a waste of time changing them.

I'm just wondering if it's okay to leave them as they are or will some assemblers (potentially one you'll be using to test with) not recognise macro/pseudo instructions, making the assembly I'm outputting incorrect as it were.

[fpgamy]

I asked the same question (in person) a few days ago and the answer was that pseudo-instructions were allowed (given that it behaves as expected upon linking with gcc).