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cy_capsense_generator_lp.h
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cy_capsense_generator_lp.h
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/***************************************************************************//**
* \file cy_capsense_generator_lp.h
* \version 5.0
*
* \brief
* This file provides the function prototypes specific to the register
* map generation module.
*
********************************************************************************
* \copyright
* Copyright 2020-2024, Cypress Semiconductor Corporation (an Infineon company)
* or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CAPSENSE_GENERATOR_LP_H)
#define CY_CAPSENSE_GENERATOR_LP_H
#include "cy_capsense_common.h"
#include "cy_capsense_structure.h"
#include "cy_capsense_sm_base_full_wave_lp.h"
#if (defined(CY_IP_M0S8MSCV3LP))
#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
* Function Prototypes
*******************************************************************************/
/******************************************************************************/
/** \cond SECTION_CAPSENSE_INTERNAL */
/** \addtogroup group_capsense_internal *//** \{ */
/******************************************************************************/
cy_capsense_status_t Cy_CapSense_GenerateBaseConfig(
cy_stc_capsense_context_t * context);
cy_capsense_status_t Cy_CapSense_GeneratePinFunctionConfig(
const cy_stc_capsense_context_t * context);
cy_capsense_status_t Cy_CapSense_GenerateSensorConfig(
uint32_t snsFrameType,
uint32_t scanSlot,
uint32_t * ptrSensorCfg,
cy_stc_capsense_context_t * context);
void Cy_CapSense_GenerateAllSensorConfig(
uint32_t snsFrameType,
cy_stc_capsense_context_t * context);
cy_capsense_status_t Cy_CapSense_GenerateCdacConfig(
const cy_stc_capsense_scan_slot_t * ptrScanSlot,
uint32_t * ptrSensorCfg,
const cy_stc_capsense_context_t * context);
void Cy_CapSense_CalculateMaskRegisters(
uint32_t mask,
uint32_t funcState,
uint32_t * ptrCfg);
uint32_t Cy_CapSense_AdjustSnsClkDivider(
uint8_t snsMethod,
uint8_t snsClkSource,
uint16_t snsClkDivider);
/** \} \endcond */
/*******************************************************************************
* Sensing modes
*******************************************************************************/
/** CSD sense mode configuration index */
#define CY_CAPSENSE_REG_MODE_CSD (0u)
/** CSX sense mode configuration index */
#define CY_CAPSENSE_REG_MODE_CSX (1u)
/** ISX sense mode configuration index */
#define CY_CAPSENSE_REG_MODE_ISX (2u)
/** CSD sense mode configuration index with CapDAC dithering enabled */
#define CY_CAPSENSE_MODE_IDX_CSD_DITHERING (3u)
/** CSX sense mode configuration index with CapDAC dithering enabled */
#define CY_CAPSENSE_MODE_IDX_CSX_DITHERING (4u)
/** ISX sense mode configuration index with CapDAC dithering enabled */
#define CY_CAPSENSE_MODE_IDX_ISX_DITHERING (5u)
/*******************************************************************************
* Sensor Config Register indexes in the frame
*******************************************************************************/
#define CY_CAPSENSE_FRM_LP_SNS_LP_AOS_SNS_CTL0 (0u)
#define CY_CAPSENSE_FRM_LP_SNS_LP_AOS_SNS_CTL1 (1u)
#define CY_CAPSENSE_FRM_LP_SNS_LP_AOS_SNS_CTL2 (2u)
#define CY_CAPSENSE_FRM_LP_SNS_LP_AOS_SNS_CTL3 (3u)
#define CY_CAPSENSE_FRM_LP_SNS_LP_AOS_SNS_CTL4 (4u)
#define CY_CAPSENSE_FRM_LP_SNS_SW_SEL_CSW_LO_MASK2_INDEX (5u)
#define CY_CAPSENSE_FRM_LP_SNS_SW_SEL_CSW_LO_MASK1_INDEX (6u)
#define CY_CAPSENSE_FRM_LP_SNS_SW_SEL_CSW_LO_MASK0_INDEX (7u)
#define CY_CAPSENSE_FRM_LP_SNS_SCAN_CTL_INDEX (8u)
#define CY_CAPSENSE_FRM_LP_SNS_CDAC_CTL_INDEX (9u)
#define CY_CAPSENSE_FRM_LP_SNS_CTL_INDEX (10u)
#define CY_CAPSENSE_SNS_SW_SEL_CSW_LO_MASK2_INDEX (0u)
#define CY_CAPSENSE_SNS_SW_SEL_CSW_LO_MASK1_INDEX (1u)
#define CY_CAPSENSE_SNS_SW_SEL_CSW_LO_MASK0_INDEX (2u)
#define CY_CAPSENSE_SNS_SCAN_CTL_INDEX (3u)
#define CY_CAPSENSE_SNS_CDAC_CTL_INDEX (4u)
#define CY_CAPSENSE_SNS_CTL_INDEX (5u)
#define CY_CAPSENSE_SNS_HW_IIR_INDEX (6u)
/*******************************************************************************
* Macros for Cmod selection
*******************************************************************************/
#define CY_CAPSENSE_CMOD12_PAIR_SELECTION (0uL)
/* CSW0 = GND */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW0_GND_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC0_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC0_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC0_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC0_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC0_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC0_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW1 = HIGH-Z */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW1_HIGH_Z_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC1_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC1_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC1_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC1_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC1_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC1_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW2 = CSX RX */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW2_CSX_RX_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC2_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC2_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC2_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC2_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC2_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC2_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW3 = CSX TX */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW3_CSX_TX_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC3_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC3_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC3_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC3_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC3_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC3_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW4 = CSX NTX */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW4_CSX_NEG_TX_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC4_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC4_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC4_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC4_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC4_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC4_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW5 = CSD SNS */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW5_CSD_SNS_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC5_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC5_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC5_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC5_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC5_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC5_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW6 = ISX LX */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW6_ISX_LX_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC6_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC6_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC6_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC6_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC6_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC6_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW7 = ISX RX */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW7_ISX_RX_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC7_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC7_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC7_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC7_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC7_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC7_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW8 = SHIELD Active */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW8_ACT_SHLD_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC8_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC8_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC8_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC8_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC8_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC8_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW9 = SHIELD Passive */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW9_PAS_SHLD_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC9_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC9_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC9_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC9_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC9_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC9_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW10 = VDDA/2 */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW10_VDDA2_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC10_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC10_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC10_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC10_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC10_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC10_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW11 = CSP */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW11_CSP_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC11_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC11_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC11_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC11_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC11_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC11_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW12 = CSN */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW12_CSN_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC12_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC12_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC12_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC12_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC12_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC12_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW13 = CSZ */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW13_CSZ_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC13_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC13_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC13_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC13_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC13_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC13_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW14 = ISX RX (two-pin cfg, internal VDDA/2) */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW14_CSZ_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC14_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC14_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC14_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC14_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC14_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC14_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW15 = ISX RX (one-pin cfg, external VDDA/2) */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW15_CSZ_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC15_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC15_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC15_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC15_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC15_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC15_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* CSW16 = ISX RX (one-pin cfg, internal VDDA/2) */
#define CY_CAPSENSE_SM_REG_SW_SEL_CSW16_CSZ_VALUE \
((CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC16_FLD_SW_AMUXA << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC16_FLD_SW_AMUXB << MSCLP_SW_SEL_CSW_FUNC_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC16_FLD_SW_PU << MSCLP_SW_SEL_CSW_FUNC_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC16_FLD_SW_PD << MSCLP_SW_SEL_CSW_FUNC_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC16_FLD_REF_MODE << MSCLP_SW_SEL_CSW_FUNC_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_SW_SEL_CSW_FUNC16_FLD_DDRV_EN << MSCLP_SW_SEL_CSW_FUNC_DDRV_EN_Pos))
/* Indexes of this values must correspond to the CY_CAPSENSE_CTRLMUX_PIN_STATE_... definitions in the common.h */
#define CY_CAPSENSE_PIN_STATES_ARR \
{CY_CAPSENSE_SM_REG_SW_SEL_CSW0_GND_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW1_HIGH_Z_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW2_CSX_RX_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW3_CSX_TX_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW4_CSX_NEG_TX_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW5_CSD_SNS_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW6_ISX_LX_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW7_ISX_RX_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW8_ACT_SHLD_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW9_PAS_SHLD_VALUE,\
CY_CAPSENSE_SM_REG_SW_SEL_CSW10_VDDA2_VALUE, \
CY_CAPSENSE_SM_REG_SW_SEL_CSW11_CSP_VALUE, \
CY_CAPSENSE_SM_REG_SW_SEL_CSW12_CSN_VALUE, \
CY_CAPSENSE_SM_REG_SW_SEL_CSW13_CSZ_VALUE}
/************************* CSD RM register values *****************************/
#define CY_CAPSENSE_CSD_RM_SENSE_DUTY_CTL \
((CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH2_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH2_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH3_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH3_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PH_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PH_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHX_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHX_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_SHIFT_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_SHIFT_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SENSE_DUTY_CTL_FLD_PHASE_MODE_SEL << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_MODE_SEL_Pos))
#define CY_CAPSENSE_CSD_RM_SW_SEL_CDAC_FL \
((CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CDAC_FL_FLD_SW_FLTCA << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CDAC_FL_FLD_SW_FLCB << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CDAC_FL_FLD_SW_FLTV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CDAC_FL_FLD_SW_FLTG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CDAC_FL_FLD_SW_FLBV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CDAC_FL_FLD_SW_FLBG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CDAC_FL_FLD_ACTIVATION_MODE << MSCLP_MODE_SW_SEL_CDAC_FL_ACTIVATION_MODE_Pos))
#if (CY_CAPSENSE_ENABLE == CY_CAPSENSE_SHIELD_ACTIVE_EN)
#define CY_CAPSENSE_CSD_RM_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_CSD_RM_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE6_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE6_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#elif (CY_CAPSENSE_ENABLE == CY_CAPSENSE_SHIELD_PASSIVE_EN)
#define CY_CAPSENSE_CSD_RM_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_CSD_RM_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE8_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE8_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#else
#define CY_CAPSENSE_CSD_RM_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_CSD_RM_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE0_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#endif /* CY_CAPSENSE_ENABLE == CY_CAPSENSE_SHIELD_ACTIVE_EN */
#define CY_CAPSENSE_CSD_RM_SW_SEL_COMP \
((CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CPCS1 << MSCLP_MODE_SW_SEL_COMP_CPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CPCS3 << MSCLP_MODE_SW_SEL_COMP_CPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CPMA << MSCLP_MODE_SW_SEL_COMP_CPMA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CPCA << MSCLP_MODE_SW_SEL_COMP_CPCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CPCB << MSCLP_MODE_SW_SEL_COMP_CPCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CMCB << MSCLP_MODE_SW_SEL_COMP_CMCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CPF << MSCLP_MODE_SW_SEL_COMP_CPF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CMCS2 << MSCLP_MODE_SW_SEL_COMP_CMCS2_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CMCS4 << MSCLP_MODE_SW_SEL_COMP_CMCS4_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CMV << MSCLP_MODE_SW_SEL_COMP_CMV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CMG << MSCLP_MODE_SW_SEL_COMP_CMG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_CMF << MSCLP_MODE_SW_SEL_COMP_CMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_COMP_FLD_HALF_WAVE_EN << MSCLP_MODE_SW_SEL_COMP_HALF_WAVE_EN_Pos))
#define CY_CAPSENSE_CSD_RM_SW_SEL_CMOD1 \
((CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD1_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD1_FLD_SW_C1CA << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD1_FLD_SW_C1CC << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD1_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD1_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD1_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD1_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD1_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD1_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD1_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD1_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD1_DDRV_EN_Pos))
#define CY_CAPSENSE_CSD_RM_SW_SEL_CMOD2 \
((CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD2_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD2_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD2_FLD_SW_C2CB << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD2_FLD_SW_C2CD << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD2_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD2_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD2_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD2_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD2_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD2_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE0_SW_SEL_CMOD2_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD2_DDRV_EN_Pos))
/************************* CSX RM register values *****************************/
#define CY_CAPSENSE_CSX_RM_SENSE_DUTY_CTL \
((CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH2_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH2_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH3_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH3_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PH_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PH_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHX_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHX_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_SHIFT_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_SHIFT_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SENSE_DUTY_CTL_FLD_PHASE_MODE_SEL << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_MODE_SEL_Pos))
#define CY_CAPSENSE_CSX_RM_SW_SEL_CDAC_FL \
((CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CDAC_FL_FLD_SW_FLTCA << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CDAC_FL_FLD_SW_FLCB << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CDAC_FL_FLD_SW_FLTV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CDAC_FL_FLD_SW_FLTG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CDAC_FL_FLD_SW_FLBV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CDAC_FL_FLD_SW_FLBG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CDAC_FL_FLD_ACTIVATION_MODE << MSCLP_MODE_SW_SEL_CDAC_FL_ACTIVATION_MODE_Pos))
#define CY_CAPSENSE_CSX_RM_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_CSX_RM_SW_SEL_COMP \
((CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CPCS1 << MSCLP_MODE_SW_SEL_COMP_CPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CPCS3 << MSCLP_MODE_SW_SEL_COMP_CPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CPMA << MSCLP_MODE_SW_SEL_COMP_CPMA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CPCA << MSCLP_MODE_SW_SEL_COMP_CPCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CPCB << MSCLP_MODE_SW_SEL_COMP_CPCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CMCB << MSCLP_MODE_SW_SEL_COMP_CMCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CPF << MSCLP_MODE_SW_SEL_COMP_CPF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CMCS2 << MSCLP_MODE_SW_SEL_COMP_CMCS2_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CMCS4 << MSCLP_MODE_SW_SEL_COMP_CMCS4_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CMV << MSCLP_MODE_SW_SEL_COMP_CMV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CMG << MSCLP_MODE_SW_SEL_COMP_CMG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_CMF << MSCLP_MODE_SW_SEL_COMP_CMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_COMP_FLD_HALF_WAVE_EN << MSCLP_MODE_SW_SEL_COMP_HALF_WAVE_EN_Pos))
#define CY_CAPSENSE_CSX_RM_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE1_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#define CY_CAPSENSE_CSX_RM_SW_SEL_CMOD1 \
((CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD1_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD1_FLD_SW_C1CA << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD1_FLD_SW_C1CC << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD1_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD1_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD1_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD1_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD1_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD1_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD1_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD1_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD1_DDRV_EN_Pos))
#define CY_CAPSENSE_CSX_RM_SW_SEL_CMOD2 \
((CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD2_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD2_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD2_FLD_SW_C2CB << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD2_FLD_SW_C2CD << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD2_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD2_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD2_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD2_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD2_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD2_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE1_SW_SEL_CMOD2_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD2_DDRV_EN_Pos))
/************************* ISX RM register values (external VDDA/2) ***********/
#define CY_CAPSENSE_ISX_RM_SENSE_DUTY_CTL \
((CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH2_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH2_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH3_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH3_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PH_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PH_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHX_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHX_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_SHIFT_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_SHIFT_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SENSE_DUTY_CTL_FLD_PHASE_MODE_SEL << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_MODE_SEL_Pos))
#define CY_CAPSENSE_ISX_RM_SW_SEL_CDAC_FL \
((CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CDAC_FL_FLD_SW_FLTCA << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CDAC_FL_FLD_SW_FLCB << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CDAC_FL_FLD_SW_FLTV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CDAC_FL_FLD_SW_FLTG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CDAC_FL_FLD_SW_FLBV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CDAC_FL_FLD_SW_FLBG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CDAC_FL_FLD_ACTIVATION_MODE << MSCLP_MODE_SW_SEL_CDAC_FL_ACTIVATION_MODE_Pos))
#define CY_CAPSENSE_ISX_RM_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_ISX_RM_SW_SEL_COMP \
((CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CPCS1 << MSCLP_MODE_SW_SEL_COMP_CPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CPCS3 << MSCLP_MODE_SW_SEL_COMP_CPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CPMA << MSCLP_MODE_SW_SEL_COMP_CPMA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CPCA << MSCLP_MODE_SW_SEL_COMP_CPCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CPCB << MSCLP_MODE_SW_SEL_COMP_CPCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CMCB << MSCLP_MODE_SW_SEL_COMP_CMCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CPF << MSCLP_MODE_SW_SEL_COMP_CPF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CMCS2 << MSCLP_MODE_SW_SEL_COMP_CMCS2_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CMCS4 << MSCLP_MODE_SW_SEL_COMP_CMCS4_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CMV << MSCLP_MODE_SW_SEL_COMP_CMV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CMG << MSCLP_MODE_SW_SEL_COMP_CMG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_CMF << MSCLP_MODE_SW_SEL_COMP_CMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_COMP_FLD_HALF_WAVE_EN << MSCLP_MODE_SW_SEL_COMP_HALF_WAVE_EN_Pos))
#define CY_CAPSENSE_ISX_RM_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE2_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#define CY_CAPSENSE_ISX_RM_SW_SEL_CMOD1 \
((CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD1_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD1_FLD_SW_C1CA << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD1_FLD_SW_C1CC << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD1_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD1_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD1_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD1_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD1_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD1_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD1_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD1_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD1_DDRV_EN_Pos))
#define CY_CAPSENSE_ISX_RM_SW_SEL_CMOD2 \
((CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD2_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD2_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD2_FLD_SW_C2CB << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD2_FLD_SW_C2CD << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD2_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD2_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD2_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD2_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD2_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD2_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE2_SW_SEL_CMOD2_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD2_DDRV_EN_Pos))
/****************** CSD RM with CapDAC dithering register values *********************/
#define CY_CAPSENSE_CSD_RM_DITHER_SENSE_DUTY_CTL \
((CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH2_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH2_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH3_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH3_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PH_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PH_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHX_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHX_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_SHIFT_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_SHIFT_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SENSE_DUTY_CTL_FLD_PHASE_MODE_SEL << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_MODE_SEL_Pos))
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_CDAC_FL \
((CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CDAC_FL_FLD_SW_FLTCA << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CDAC_FL_FLD_SW_FLCB << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CDAC_FL_FLD_SW_FLTV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CDAC_FL_FLD_SW_FLTG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CDAC_FL_FLD_SW_FLBV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CDAC_FL_FLD_SW_FLBG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CDAC_FL_FLD_ACTIVATION_MODE << MSCLP_MODE_SW_SEL_CDAC_FL_ACTIVATION_MODE_Pos))
#if (CY_CAPSENSE_ENABLE == CY_CAPSENSE_SHIELD_ACTIVE_EN)
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE7_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE7_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#elif (CY_CAPSENSE_ENABLE == CY_CAPSENSE_SHIELD_PASSIVE_EN)
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE9_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE9_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#else
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE3_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#endif /* CY_CAPSENSE_ENABLE == CY_CAPSENSE_SHIELD_ACTIVE_EN */
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_COMP \
((CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CPCS1 << MSCLP_MODE_SW_SEL_COMP_CPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CPCS3 << MSCLP_MODE_SW_SEL_COMP_CPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CPMA << MSCLP_MODE_SW_SEL_COMP_CPMA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CPCA << MSCLP_MODE_SW_SEL_COMP_CPCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CPCB << MSCLP_MODE_SW_SEL_COMP_CPCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CMCB << MSCLP_MODE_SW_SEL_COMP_CMCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CPF << MSCLP_MODE_SW_SEL_COMP_CPF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CMCS2 << MSCLP_MODE_SW_SEL_COMP_CMCS2_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CMCS4 << MSCLP_MODE_SW_SEL_COMP_CMCS4_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CMV << MSCLP_MODE_SW_SEL_COMP_CMV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CMG << MSCLP_MODE_SW_SEL_COMP_CMG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_CMF << MSCLP_MODE_SW_SEL_COMP_CMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_COMP_FLD_HALF_WAVE_EN << MSCLP_MODE_SW_SEL_COMP_HALF_WAVE_EN_Pos))
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_CMOD1 \
((CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD1_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD1_FLD_SW_C1CA << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD1_FLD_SW_C1CC << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD1_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD1_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD1_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD1_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD1_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD1_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD1_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD1_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD1_DDRV_EN_Pos))
#define CY_CAPSENSE_CSD_RM_DITHER_SW_SEL_CMOD2 \
((CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD2_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD2_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD2_FLD_SW_C2CB << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD2_FLD_SW_C2CD << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD2_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD2_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD2_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD2_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD2_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD2_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE3_SW_SEL_CMOD2_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD2_DDRV_EN_Pos))
/****************** CSX RM with CapDAC dithering register values *********************/
#define CY_CAPSENSE_CSX_RM_DITHER_SENSE_DUTY_CTL \
((CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH2_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH2_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH3_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH3_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PH_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PH_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHX_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHX_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_SHIFT_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_SHIFT_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SENSE_DUTY_CTL_FLD_PHASE_MODE_SEL << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_MODE_SEL_Pos))
#define CY_CAPSENSE_CSX_RM_DITHER_SW_SEL_CDAC_FL \
((CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CDAC_FL_FLD_SW_FLTCA << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CDAC_FL_FLD_SW_FLCB << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CDAC_FL_FLD_SW_FLTV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CDAC_FL_FLD_SW_FLTG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CDAC_FL_FLD_SW_FLBV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CDAC_FL_FLD_SW_FLBG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CDAC_FL_FLD_ACTIVATION_MODE << MSCLP_MODE_SW_SEL_CDAC_FL_ACTIVATION_MODE_Pos))
#define CY_CAPSENSE_CSX_RM_DITHER_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_CSX_RM_DITHER_SW_SEL_COMP \
((CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CPCS1 << MSCLP_MODE_SW_SEL_COMP_CPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CPCS3 << MSCLP_MODE_SW_SEL_COMP_CPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CPMA << MSCLP_MODE_SW_SEL_COMP_CPMA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CPCA << MSCLP_MODE_SW_SEL_COMP_CPCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CPCB << MSCLP_MODE_SW_SEL_COMP_CPCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CMCB << MSCLP_MODE_SW_SEL_COMP_CMCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CPF << MSCLP_MODE_SW_SEL_COMP_CPF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CMCS2 << MSCLP_MODE_SW_SEL_COMP_CMCS2_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CMCS4 << MSCLP_MODE_SW_SEL_COMP_CMCS4_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CMV << MSCLP_MODE_SW_SEL_COMP_CMV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CMG << MSCLP_MODE_SW_SEL_COMP_CMG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_CMF << MSCLP_MODE_SW_SEL_COMP_CMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_COMP_FLD_HALF_WAVE_EN << MSCLP_MODE_SW_SEL_COMP_HALF_WAVE_EN_Pos))
#define CY_CAPSENSE_CSX_RM_DITHER_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE4_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#define CY_CAPSENSE_CSX_RM_DITHER_SW_SEL_CMOD1 \
((CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD1_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD1_FLD_SW_C1CA << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD1_FLD_SW_C1CC << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD1_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD1_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD1_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD1_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD1_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD1_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD1_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD1_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD1_DDRV_EN_Pos))
#define CY_CAPSENSE_CSX_RM_DITHER_SW_SEL_CMOD2 \
((CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD2_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD2_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD2_FLD_SW_C2CB << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD2_FLD_SW_C2CD << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD2_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD2_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD2_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD2_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD2_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD2_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE4_SW_SEL_CMOD2_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD2_DDRV_EN_Pos))
/****************** ISX RM with CapDAC dithering register values (external VDDA/2) */
#define CY_CAPSENSE_ISX_RM_DITHER_SENSE_DUTY_CTL \
((CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH2_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH2_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH3_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH3_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PH_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PH_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHX_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHX_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_SHIFT_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_SHIFT_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SENSE_DUTY_CTL_FLD_PHASE_MODE_SEL << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_MODE_SEL_Pos))
#define CY_CAPSENSE_ISX_RM_DITHER_SW_SEL_CDAC_FL \
((CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CDAC_FL_FLD_SW_FLTCA << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CDAC_FL_FLD_SW_FLCB << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CDAC_FL_FLD_SW_FLTV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CDAC_FL_FLD_SW_FLTG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CDAC_FL_FLD_SW_FLBV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CDAC_FL_FLD_SW_FLBG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CDAC_FL_FLD_ACTIVATION_MODE << MSCLP_MODE_SW_SEL_CDAC_FL_ACTIVATION_MODE_Pos))
#define CY_CAPSENSE_ISX_RM_DITHER_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_ISX_RM_DITHER_SW_SEL_COMP \
((CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CPCS1 << MSCLP_MODE_SW_SEL_COMP_CPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CPCS3 << MSCLP_MODE_SW_SEL_COMP_CPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CPMA << MSCLP_MODE_SW_SEL_COMP_CPMA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CPCA << MSCLP_MODE_SW_SEL_COMP_CPCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CPCB << MSCLP_MODE_SW_SEL_COMP_CPCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CMCB << MSCLP_MODE_SW_SEL_COMP_CMCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CPF << MSCLP_MODE_SW_SEL_COMP_CPF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CMCS2 << MSCLP_MODE_SW_SEL_COMP_CMCS2_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CMCS4 << MSCLP_MODE_SW_SEL_COMP_CMCS4_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CMV << MSCLP_MODE_SW_SEL_COMP_CMV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CMG << MSCLP_MODE_SW_SEL_COMP_CMG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_CMF << MSCLP_MODE_SW_SEL_COMP_CMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_COMP_FLD_HALF_WAVE_EN << MSCLP_MODE_SW_SEL_COMP_HALF_WAVE_EN_Pos))
#define CY_CAPSENSE_ISX_RM_DITHER_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE5_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#define CY_CAPSENSE_ISX_RM_DITHER_SW_SEL_CMOD1 \
((CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD1_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD1_FLD_SW_C1CA << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD1_FLD_SW_C1CC << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD1_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD1_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD1_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD1_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD1_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD1_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD1_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD1_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD1_DDRV_EN_Pos))
#define CY_CAPSENSE_ISX_RM_DITHER_SW_SEL_CMOD2 \
((CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD2_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD2_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD2_FLD_SW_C2CB << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD2_FLD_SW_C2CD << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD2_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD2_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD2_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD2_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD2_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD2_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE5_SW_SEL_CMOD2_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD2_DDRV_EN_Pos))
/************************* MPSC RM register values *****************************/
#define CY_CAPSENSE_MPSC_RM_SENSE_DUTY_CTL \
((CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH2_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH2_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH3_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH3_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PH_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PH_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHX_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHX_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_SHIFT_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_SHIFT_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SENSE_DUTY_CTL_FLD_PHASE_MODE_SEL << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_MODE_SEL_Pos))
#define CY_CAPSENSE_MPSC_RM_SW_SEL_CDAC_FL \
((CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CDAC_FL_FLD_SW_FLTCA << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CDAC_FL_FLD_SW_FLCB << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CDAC_FL_FLD_SW_FLTV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CDAC_FL_FLD_SW_FLTG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CDAC_FL_FLD_SW_FLBV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CDAC_FL_FLD_SW_FLBG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CDAC_FL_FLD_ACTIVATION_MODE << MSCLP_MODE_SW_SEL_CDAC_FL_ACTIVATION_MODE_Pos))
#define CY_CAPSENSE_MPSC_RM_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_MPSC_RM_SW_SEL_COMP \
((CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CPCS1 << MSCLP_MODE_SW_SEL_COMP_CPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CPCS3 << MSCLP_MODE_SW_SEL_COMP_CPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CPMA << MSCLP_MODE_SW_SEL_COMP_CPMA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CPCA << MSCLP_MODE_SW_SEL_COMP_CPCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CPCB << MSCLP_MODE_SW_SEL_COMP_CPCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CMCB << MSCLP_MODE_SW_SEL_COMP_CMCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CPF << MSCLP_MODE_SW_SEL_COMP_CPF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CMCS2 << MSCLP_MODE_SW_SEL_COMP_CMCS2_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CMCS4 << MSCLP_MODE_SW_SEL_COMP_CMCS4_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CMV << MSCLP_MODE_SW_SEL_COMP_CMV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CMG << MSCLP_MODE_SW_SEL_COMP_CMG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_CMF << MSCLP_MODE_SW_SEL_COMP_CMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_COMP_FLD_HALF_WAVE_EN << MSCLP_MODE_SW_SEL_COMP_HALF_WAVE_EN_Pos))
#define CY_CAPSENSE_MPSC_RM_SW_SEL_SH \
((CY_CAPSENSE_SM_REG_MODE10_SW_SEL_SH_FLD_SOMB << MSCLP_MODE_SW_SEL_SH_SOMB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_SH_FLD_CBSO << MSCLP_MODE_SW_SEL_SH_CBSO_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_SH_FLD_SPCS1 << MSCLP_MODE_SW_SEL_SH_SPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_SH_FLD_SPCS3 << MSCLP_MODE_SW_SEL_SH_SPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_SH_FLD_FSP << MSCLP_MODE_SW_SEL_SH_FSP_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_SH_FLD_BUF_SEL << MSCLP_MODE_SW_SEL_SH_BUF_SEL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_SH_FLD_BUF_EN << MSCLP_MODE_SW_SEL_SH_BUF_EN_Pos))
#define CY_CAPSENSE_MPSC_RM_SW_SEL_CMOD1 \
((CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD1_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD1_FLD_SW_C1CA << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD1_FLD_SW_C1CC << MSCLP_MODE_SW_SEL_CMOD1_SW_C1CC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD1_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD1_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD1_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD1_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD1_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD1_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD1_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD1_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD1_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD1_DDRV_EN_Pos))
#define CY_CAPSENSE_MPSC_RM_SW_SEL_CMOD2 \
((CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD2_FLD_SW_AMUXA << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD2_FLD_SW_AMUXB << MSCLP_MODE_SW_SEL_CMOD2_SW_AMUXB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD2_FLD_SW_C2CB << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD2_FLD_SW_C2CD << MSCLP_MODE_SW_SEL_CMOD2_SW_C2CD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD2_FLD_SW_PU << MSCLP_MODE_SW_SEL_CMOD2_SW_PU_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD2_FLD_SW_PD << MSCLP_MODE_SW_SEL_CMOD2_SW_PD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD2_FLD_REF_MODE << MSCLP_MODE_SW_SEL_CMOD2_REF_MODE_Pos) | \
(CY_CAPSENSE_SM_REG_MODE10_SW_SEL_CMOD2_FLD_DDRV_EN << MSCLP_MODE_SW_SEL_CMOD2_DDRV_EN_Pos))
/************************* MPSC RM with CapDAC dithering register values *****************************/
#define CY_CAPSENSE_MPSC_RM_DITHER_SENSE_DUTY_CTL \
((CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH2_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH2_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH3_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH3_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH0_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH0_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_GAP_FS2_PH1_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_FS2_PH1_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PH_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PH_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH0X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH0X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_GAP_PH1X_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_GAP_PH1X_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHX_GAP_2CYCLE_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHX_GAP_2CYCLE_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_SHIFT_EN << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_SHIFT_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SENSE_DUTY_CTL_FLD_PHASE_MODE_SEL << MSCLP_MODE_SENSE_DUTY_CTL_PHASE_MODE_SEL_Pos))
#define CY_CAPSENSE_MPSC_RM_DITHER_SW_SEL_CDAC_FL \
((CY_CAPSENSE_SM_REG_MODE11_SW_SEL_CDAC_FL_FLD_SW_FLTCA << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_CDAC_FL_FLD_SW_FLCB << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_CDAC_FL_FLD_SW_FLTV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_CDAC_FL_FLD_SW_FLTG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLTG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_CDAC_FL_FLD_SW_FLBV << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBV_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_CDAC_FL_FLD_SW_FLBG << MSCLP_MODE_SW_SEL_CDAC_FL_SW_FLBG_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_CDAC_FL_FLD_ACTIVATION_MODE << MSCLP_MODE_SW_SEL_CDAC_FL_ACTIVATION_MODE_Pos))
#define CY_CAPSENSE_MPSC_RM_DITHER_SW_SEL_TOP \
((CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_CACB << MSCLP_MODE_SW_SEL_TOP_CACB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_CACC << MSCLP_MODE_SW_SEL_TOP_CACC_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_CBCD << MSCLP_MODE_SW_SEL_TOP_CBCD_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_AYA_CTL << MSCLP_MODE_SW_SEL_TOP_AYA_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_AYA_EN << MSCLP_MODE_SW_SEL_TOP_AYA_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_AYB_CTL << MSCLP_MODE_SW_SEL_TOP_AYB_CTL_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_AYB_EN << MSCLP_MODE_SW_SEL_TOP_AYB_EN_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_BYB << MSCLP_MODE_SW_SEL_TOP_BYB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_BGRF << MSCLP_MODE_SW_SEL_TOP_BGRF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_RMF << MSCLP_MODE_SW_SEL_TOP_RMF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_TOP_FLD_MBF << MSCLP_MODE_SW_SEL_TOP_MBF_Pos))
#define CY_CAPSENSE_MPSC_RM_DITHER_SW_SEL_COMP \
((CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CPCS1 << MSCLP_MODE_SW_SEL_COMP_CPCS1_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CPCS3 << MSCLP_MODE_SW_SEL_COMP_CPCS3_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CPMA << MSCLP_MODE_SW_SEL_COMP_CPMA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CPCA << MSCLP_MODE_SW_SEL_COMP_CPCA_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CPCB << MSCLP_MODE_SW_SEL_COMP_CPCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CMCB << MSCLP_MODE_SW_SEL_COMP_CMCB_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CPF << MSCLP_MODE_SW_SEL_COMP_CPF_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CMCS2 << MSCLP_MODE_SW_SEL_COMP_CMCS2_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CMCS4 << MSCLP_MODE_SW_SEL_COMP_CMCS4_Pos) | \
(CY_CAPSENSE_SM_REG_MODE11_SW_SEL_COMP_FLD_CMV << MSCLP_MODE_SW_SEL_COMP_CMV_Pos) | \