verilog serializer

[Nic30]

No description provided.

[Nic30]

depends on #6

[Nic30]

I was thinking we could use jinja2 templates for HDL generating and thus greatly reduce development time and improve flexibility and shrink codebase. However all Jinja2 libraries for C++, which I have found, do have some problem.

https://github.com/pantor/inja

• non standard json library
• definitions in header files, preventing from use in multiple cpp files

https://github.com/flexferrum/Jinja2Cpp

• broken cmake modified to suit only one project
• depends on multiple libraries which have to be downloaded from the git or by conan
• conan build non compatible with meson

https://github.com/hughperkins/Jinja2CppLight

• too limited support of Jinja2 (e.g. it does not supports even if statement )

Maybe I am just bad at searching but I did not find anything else and I can not fix Jinja2Cpp because they do not want to, I do not have time to fix Inja or implement Jinja2CppLight.

So the template of the HDL feature (e.g. if statement) will be implemented in virtual method of the serializer.

[Nic30]

simple module serialization working https://github.com/HardwareIR/netlistDB/blob/4e366e5b4adbf3797e87691251ac0c630f3cfaef/tests/verilog_simple_modules_test.cpp

What should work:

• serialization of statements, operators nets, module body and header
  • [done] missing test for proper brace resolution based on precedence
  • [done] missing serialization of the types!
  • [done] missing serialization of internal signals in the module
  • [done] missing serialization of the component maps
  • [done] missing range operators
  • missing ternary operator
• the processes are prettified and merged if they share same branching structure
  • more tests required
• the output is deterministic (even if sets are used for many things)
  • tests required
• names should be checked and _n should be added if name is colliding
  • tests required
  • the name checking scope probably does not have set scope correctly and names
    are maybe checked on places where they does not have to be
• the expression which are not supported by Verilog are extracted as a tmp variable (arithmetic in concatenation etc.)
  • tests requiered
• the event operators in if statement is extracted to sensitivity list
  • clock gating not implemented (if condition signal is more than event operator it is not replaced correctly)
  • async register reset edge detection not implemented
• [done] missing serialization machinery which will generate proper file structure for the hierarchical design.

[Nic30]

• missing serialization machinery which will generate proper file structure for the hierarchical design.

[done] this requires to put output stream reference to the serializer object properties and switch the output stream to new file if the new module is serialized