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Optimize Power Consumption (Sleep) #3

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JohnAZoidberg opened this issue Feb 16, 2023 · 3 comments
Open
3 of 9 tasks

Optimize Power Consumption (Sleep) #3

JohnAZoidberg opened this issue Feb 16, 2023 · 3 comments
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pvt Has to be ready for PVT/FATP

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@JohnAZoidberg
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JohnAZoidberg commented Feb 16, 2023

Steps:

  1. Try deep-sleep
  2. Measure power with only LEDs, no USB
  3. Try interrupt based USB. Can USB wake us from dormant or sleep?

Sleep/Dormant

System sleep mode is entered automatically when both cores are in sleep and the DMA has no outstanding
transactions. In system sleep mode, the clock enables described in the previous paragraphs are switched from the
WAKE_EN registers to the SLEEP_EN registers. The intention is to reduce power consumed in the clock distribution networks
when the chip is inactive. If the user has not configured the WAKE_EN and SLEEP_EN registers then system sleep will do
nothing.

RP2040 enters the SLEEP state when all of the following are true:
• Both processors are asleep (e.g. in a WFE or WFI instruction)
• The system DMA has no outstanding transfers on any channel
RP2040 exits the SLEEP state when either processor is awoken by an interrupt.

Clocks

The clock generators select from the clock sources and optionally divide the selected clock before outputting through
enable logic which provides automatic clock disabling in SLEEP mode (see Section 2.11.2).

The chip has an ultra-low power mode called DORMANT (see Section 2.11.3) in which all on-chip clock sources are
stopped to save power. External sources are not stopped and can be used to provide a clock to the on-chip RTC which
can provide an alarm to wake the chip from DORMANT mode. Alternatively the GPIO interrupts can be configured to
wake the chip from DORMANT mode in response to an external event.

If an external clock or the XOSC is used then the ROSC can be stopped to save power. However, the reference clock
generator and the system clock generator must be switched to an alternate source before doing so.

The XOSC is not affected by SLEEP mode. It is automatically stopped and restarted in the same configuration when
entering and exiting DORMANT mode.

The PLLs are not affected by SLEEP mode. If the user wants to save power in SLEEP mode then all clock generators
must be switched away from the PLLs and they must be stopped in software before entering SLEEP mode. The PLLs
are not stopped and restarted automatically when entering and exiting DORMANT mode. If they are left running on entry
to DORMANT mode they will be corrupted and will generate out of control clocks that will consume power
unnecessarily. This happens because their reference clock from XOSC will be stopped. It is therefore essential to switch
all clock generators away from the PLLs and stop the PLLs in software before entering DORMANT mode.

@JohnAZoidberg JohnAZoidberg mentioned this issue Feb 20, 2023
22 tasks
@JohnAZoidberg JohnAZoidberg added the pvt Has to be ready for PVT/FATP label Mar 7, 2023
@JohnAZoidberg JohnAZoidberg changed the title Optimize Power Consumption Optimize Power Consumption (Sleep) Mar 7, 2023
@JohnAZoidberg JohnAZoidberg self-assigned this Mar 28, 2023
@JohnAZoidberg
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@OctopusET
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This PR is merged rp-rs/rp-hal#676
related issue: rp-rs/rp-hal#659

@JohnAZoidberg
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Support for dormant mode merged now: rp-rs/rp-hal#701

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