From 87be1ff9ff477b6fdb13de059ce17d28c61911d7 Mon Sep 17 00:00:00 2001 From: Nicolas Cuervo Date: Wed, 14 Mar 2018 21:58:54 +0100 Subject: [PATCH 1/5] Remove instances of tap_update --- grc/pfb_channelizer_tap_update.xml | 35 ----- python/CMakeLists.txt | 3 +- python/tap_update.py | 220 ----------------------------- 3 files changed, 1 insertion(+), 257 deletions(-) delete mode 100644 grc/pfb_channelizer_tap_update.xml delete mode 100644 python/tap_update.py diff --git a/grc/pfb_channelizer_tap_update.xml b/grc/pfb_channelizer_tap_update.xml deleted file mode 100644 index 7f75429..0000000 --- a/grc/pfb_channelizer_tap_update.xml +++ /dev/null @@ -1,35 +0,0 @@ - - - tap_update - pfb_channelizer_tap_update - [pfb_channelizer] - import pfb_channelizer - pfb_channelizer.tap_update() -self.$(id).initialize($fft_size) - - - send_taps($fft_size) - - - FFT Size - fft_size - 128 - int - - - - to_rfnoc - message - 1 - - - - diff --git a/python/CMakeLists.txt b/python/CMakeLists.txt index 2aa6841..6f40d9d 100644 --- a/python/CMakeLists.txt +++ b/python/CMakeLists.txt @@ -31,10 +31,9 @@ endif() GR_PYTHON_INSTALL( FILES __init__.py - tap_update.py DESTINATION ${GR_PYTHON_DIR}/pfb_channelizer + DESTINATION ${GR_PYTHON_DIR}/pfb_channelizer ) -# tap_update.py ######################################################################## # Handle the unit tests ######################################################################## diff --git a/python/tap_update.py b/python/tap_update.py deleted file mode 100644 index 6d41779..0000000 --- a/python/tap_update.py +++ /dev/null @@ -1,220 +0,0 @@ -#!/usr/bin/env python -# -*- coding: utf-8 -*- -# -# Copyright 2017 <+YOU OR YOUR COMPANY+>. -# -# This is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# This software is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this software; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -import numpy as np -import copy -import pmt -import sys -import time -import threading -from gnuradio import gr - -six_db = 10 * np.log10(.25) - -class tap_update(gr.sync_block): - """ - docstring for block tap_update - """ - def __init__(self): - gr.sync_block.__init__(self, name="tap_update", in_sig=None, out_sig=None) - - self.last_sent = 0 - self.finished = False - self.K = 10.519 - self.message_port_register_out(pmt.intern('to_rfnoc')) - self.max_fft_size = 512 - self.qvec_coef = (25, 24) - self.qvec = (18, 17) - self.taps_per_phase = 24 - self.old_size = 0 - self.fft_size = 0 - self.taps_set = False - - self.thread = threading.Thread(target=self.settap_thread) - self.thread.daemon = True - self.thread.start() - - def stop(self): - self.thread.join() - self.finished = True - return gr.sync_block.stop(self) - - def erfc(self, x): - # save the sign of x - sign = [1 if val >= 0 else -1 for val in x] - x = abs(x) - - # constants - a1 = 0.254829592 - a2 = -0.284496736 - a3 = 1.421413741 - a4 = -1.453152027 - a5 = 1.061405429 - p = 0.3275911 - - # A&S formula 7.1.26 - t = 1.0/(1.0 + p*x) - y = 1.0 - (((((a5*t + a4)*t) + a3)*t + a2)*t + a1)*t*np.exp(-x*x) - ret_val = 1 - sign*y - return ret_val - - def nextpow2(self, i): - """ - Find 2^n that is equal to or greater than. - """ - n = 0 - while (2**n) < i: - n += 1 - return n - - def ret_num_bitsU(self, value): - ''' - Function returns required number of bits for unsigned binary - representation. - ''' - val_new = np.floor(value) - - if value == 0: - return 1 - - temp = np.ceil(np.log2(np.abs(val_new + .5))) - return temp.astype(np.int) - - def ret_num_bitsS(self, value): - ''' - Function returns required number of bits for 2's - complement representation. - ''' - if value < 0: - temp = self.ret_num_bitsU(np.abs(value) - 1) - else: - temp = self.ret_num_bitsU(value) + 1 - return temp - - def tap_equation(self, fft_size): - F = np.arange(self.taps_per_phase * fft_size) - F = np.double(F) / len(F) - - x = self.K * (np.double(fft_size) * F - .5) - A = np.sqrt(0.5 * self.erfc(x)) - - N = len(A) - - idx = np.arange(N / 2) - A[N - idx - 1] = np.conj(A[1 + idx]) - A[N // 2] = 0 - - db_diff = six_db - 10 * np.log10(.5) - exponent = 10. ** (-db_diff / 10.) - - A = A ** exponent - - b = np.fft.ifft(A) - b = (np.fft.fftshift(b)).real - - b /= np.sum(b) - - return b - - def gen_fixed_filter(self, taps, fft_size, desired_msb=40): - - max_coeff_val = (2. **(self.qvec_coef[0] - 1) - 1) * (2. ** -self.qvec_coef[1]) - - taps_gain = max_coeff_val / np.max(np.abs(taps)) - taps *= taps_gain - taps_fi = (taps * (2. ** self.qvec_coef[1])).astype(np.int) - poly_fil = np.reshape(taps_fi, (fft_size, -1), order='F') - - max_input = int(2.**(self.qvec[0] - 1)) - 1 - # compute noise and signal gain. - s_gain = np.abs(np.max(np.sum(poly_fil, axis=1))) - - gain_msb = self.nextpow2(s_gain) - max_coef_val = 2. ** gain_msb - 1 - in_use = s_gain / max_coef_val - # print(np.max(s_gain), np.max(max_input)) - max_value = np.max(s_gain).astype(np.int64) * np.max(max_input).astype(np.int64) - num_bits = self.ret_num_bitsS(max_value) - # print(num_bits) - msb = num_bits - 1 - if in_use > .9: - new_b = poly_fil - delta_gain = 1 - else: - # note we are scaling down here hence the - 1 - msb = msb - 1 - delta_gain = .5 * (max_coef_val / s_gain) - new_b = np.floor(poly_fil * delta_gain).astype(int) - - poly_fil = new_b - if desired_msb is not None: - if msb > desired_msb: - diff = msb - desired_msb - poly_fil = poly_fil >> diff - msb = desired_msb - - # print("msb = {}".format(msb)) - # taps_fi = np.reshape(poly_fil, (1, -1), order='F') - poly_fil = poly_fil.astype(np.int32) - - return poly_fil - - def gen_tap_vec(self, poly_fil, fft_size): - """ - Helper function that generates a single vector used for programming - the internal ram - """ - pfb_fil = copy.deepcopy(poly_fil) - pfb_fil = pfb_fil.T - # qvec = (self.qvec_coef[0], 0) - vec = np.array([]) - pad = np.array([0] * (self.max_fft_size - fft_size)) - for col in pfb_fil: - col_vec = np.concatenate((col, pad)) - vec = np.concatenate((vec, col_vec)) - - return vec.astype(np.int) - - def initialize(self, fft_size): - self.fft_size = fft_size - - def send_taps(self, fft_size): - - self.fft_size = fft_size - self.taps_set = True - taps = self.tap_equation(fft_size) - taps_fi = self.gen_fixed_filter(taps, fft_size) - taps_vec = self.gen_tap_vec(taps_fi, fft_size) - data_rfnoc = pmt.init_s32vector(len(taps_vec), taps_vec.tolist()) - msg = pmt.cons(pmt.get_PMT_NIL(), data_rfnoc) - # print(msg) - self.message_port_pub( - pmt.intern('to_rfnoc'), msg) - print("done sending") - - def settap_thread(self): - time.sleep(3) - while(self.fft_size == 0): - time.sleep(.1) - if self.taps_set is False: - self.send_taps(self.fft_size) - - return 0 From 5000cacf00bb8eff4f7dba58db0db834157bab81 Mon Sep 17 00:00:00 2001 From: Nicolas Cuervo Date: Wed, 14 Mar 2018 22:54:21 +0100 Subject: [PATCH 2/5] Removed noc_block_chanmux --- rfnoc/fpga-src/Makefile.inc | 1 - rfnoc/fpga-src/Makefile.srcs | 1 - rfnoc/fpga-src/noc_block_chanmux.v | 182 ------------------ rfnoc/testbenches/CMakeLists.txt | 1 - .../noc_block_chanmux_tb/CMakeLists.txt | 1 - .../testbenches/noc_block_chanmux_tb/Makefile | 34 ---- .../noc_block_chanmux_tb.sv | 100 ---------- 7 files changed, 320 deletions(-) delete mode 100644 rfnoc/fpga-src/noc_block_chanmux.v delete mode 100644 rfnoc/testbenches/noc_block_chanmux_tb/CMakeLists.txt delete mode 100644 rfnoc/testbenches/noc_block_chanmux_tb/Makefile delete mode 100644 rfnoc/testbenches/noc_block_chanmux_tb/noc_block_chanmux_tb.sv diff --git a/rfnoc/fpga-src/Makefile.inc b/rfnoc/fpga-src/Makefile.inc index 85b4599..7401c3c 100644 --- a/rfnoc/fpga-src/Makefile.inc +++ b/rfnoc/fpga-src/Makefile.inc @@ -3,7 +3,6 @@ ################################################## RFNOC_SRCS += $(addprefix $(RFNOC_PFB_CHANNELIZER_DIR)/fpga-src/, \ -noc_block_chanmux.v \ count_cycle_iw36_cw11.v \ count_items_iw36_cw11.v \ input_buffer.v \ diff --git a/rfnoc/fpga-src/Makefile.srcs b/rfnoc/fpga-src/Makefile.srcs index 501aa2c..6a731d5 100644 --- a/rfnoc/fpga-src/Makefile.srcs +++ b/rfnoc/fpga-src/Makefile.srcs @@ -1,5 +1,4 @@ $(addprefix SOURCES_PATH, \ -noc_block_chanmux.v \ count_cycle_iw36_cw11.v \ count_items_iw36_cw11.v \ input_buffer.v \ diff --git a/rfnoc/fpga-src/noc_block_chanmux.v b/rfnoc/fpga-src/noc_block_chanmux.v deleted file mode 100644 index 6a77e18..0000000 --- a/rfnoc/fpga-src/noc_block_chanmux.v +++ /dev/null @@ -1,182 +0,0 @@ - -// -// Copyright 2015 Ettus Research -// -module noc_block_chanmux #( - parameter NOC_ID = 64'hF2A3373CFBFB4BFA, - parameter STR_SINK_FIFOSIZE = 11) -( - input bus_clk, input bus_rst, - input ce_clk, input ce_rst, - input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, - output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready, - output [63:0] debug -); - - //////////////////////////////////////////////////////////// - // - // RFNoC Shell - // - //////////////////////////////////////////////////////////// - wire [31:0] set_data; - wire [7:0] set_addr; - wire set_stb; - reg [63:0] rb_data; - wire [7:0] rb_addr; - - wire [63:0] cmdout_tdata, ackin_tdata; - wire cmdout_tlast, cmdout_tvalid, cmdout_tready, ackin_tlast, ackin_tvalid, ackin_tready; - - wire [63:0] str_sink_tdata, str_src_tdata; - wire str_sink_tlast, str_sink_tvalid, str_sink_tready, str_src_tlast, str_src_tvalid, str_src_tready; - - wire [15:0] src_sid; - wire [15:0] next_dst_sid, resp_out_dst_sid; - wire [15:0] resp_in_dst_sid; - - wire clear_tx_seqnum; - - noc_shell #( - .NOC_ID(NOC_ID), - .STR_SINK_FIFOSIZE(STR_SINK_FIFOSIZE)) - noc_shell ( - .bus_clk(bus_clk), .bus_rst(bus_rst), - .i_tdata(i_tdata), .i_tlast(i_tlast), .i_tvalid(i_tvalid), .i_tready(i_tready), - .o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready), - // Computer Engine Clock Domain - .clk(ce_clk), .reset(ce_rst), - // Control Sink - .set_data(set_data), .set_addr(set_addr), .set_stb(set_stb), - .rb_stb(1'b1), .rb_data(rb_data), .rb_addr(rb_addr), - // Control Source - .cmdout_tdata(cmdout_tdata), .cmdout_tlast(cmdout_tlast), .cmdout_tvalid(cmdout_tvalid), .cmdout_tready(cmdout_tready), - .ackin_tdata(ackin_tdata), .ackin_tlast(ackin_tlast), .ackin_tvalid(ackin_tvalid), .ackin_tready(ackin_tready), - // Stream Sink - .str_sink_tdata(str_sink_tdata), .str_sink_tlast(str_sink_tlast), .str_sink_tvalid(str_sink_tvalid), .str_sink_tready(str_sink_tready), - // Stream Source - .str_src_tdata(str_src_tdata), .str_src_tlast(str_src_tlast), .str_src_tvalid(str_src_tvalid), .str_src_tready(str_src_tready), - // Stream IDs set by host - .src_sid(src_sid), // SID of this block - .next_dst_sid(next_dst_sid), // Next destination SID - .resp_in_dst_sid(resp_in_dst_sid), // Response destination SID for input stream responses / errors - .resp_out_dst_sid(resp_out_dst_sid), // Response destination SID for output stream responses / errors - // Misc - .vita_time('d0), .clear_tx_seqnum(clear_tx_seqnum), - .debug(debug)); - - //////////////////////////////////////////////////////////// - // - // AXI Wrapper - // Convert RFNoC Shell interface into AXI stream interface - // - //////////////////////////////////////////////////////////// - wire [31:0] m_axis_data_tdata; - wire m_axis_data_tlast; - wire m_axis_data_tvalid; - wire m_axis_data_tready; - - wire [31:0] s_axis_data_tdata; - wire s_axis_data_tlast; - wire s_axis_data_tvalid; - wire s_axis_data_tready; - - axi_wrapper #( - .SIMPLE_MODE(1)) - axi_wrapper ( - .clk(ce_clk), .reset(ce_rst), - .clear_tx_seqnum(clear_tx_seqnum), - .next_dst(next_dst_sid), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .i_tdata(str_sink_tdata), .i_tlast(str_sink_tlast), .i_tvalid(str_sink_tvalid), .i_tready(str_sink_tready), - .o_tdata(str_src_tdata), .o_tlast(str_src_tlast), .o_tvalid(str_src_tvalid), .o_tready(str_src_tready), - .m_axis_data_tdata(m_axis_data_tdata), - .m_axis_data_tlast(m_axis_data_tlast), - .m_axis_data_tvalid(m_axis_data_tvalid), - .m_axis_data_tready(m_axis_data_tready), - .m_axis_data_tuser(), - .s_axis_data_tdata(s_axis_data_tdata), - .s_axis_data_tlast(s_axis_data_tlast), - .s_axis_data_tvalid(s_axis_data_tvalid), - .s_axis_data_tready(s_axis_data_tready), - .s_axis_data_tuser(), - .m_axis_config_tdata(), - .m_axis_config_tlast(), - .m_axis_config_tvalid(), - .m_axis_config_tready(), - .m_axis_pkt_len_tdata(), - .m_axis_pkt_len_tvalid(), - .m_axis_pkt_len_tready()); - - //////////////////////////////////////////////////////////// - // - // User code - // - //////////////////////////////////////////////////////////// - // NoC Shell registers 0 - 127, - // User register address space starts at 128 - localparam SR_USER_REG_BASE = 128; - - // Control Source Unused - assign cmdout_tdata = 64'd0; - assign cmdout_tlast = 1'b0; - assign cmdout_tvalid = 1'b0; - assign ackin_tready = 1'b1; - - // Settings registers - // - // - The settings register bus is a simple strobed interface. - // - Transactions include both a write and a readback. - // - The write occurs when set_stb is asserted. - // The settings register with the address matching set_addr will - // be loaded with the data on set_data. - // - Readback occurs when rb_stb is asserted. The read back strobe - // must assert at least one clock cycle after set_stb asserts / - // rb_stb is ignored if asserted on the same clock cycle of set_stb. - // Example valid and invalid timing: - // __ __ __ __ - // clk __| |__| |__| |__| |__ - // _____ - // set_stb ___| |________________ - // _____ - // rb_stb _________| |__________ (Valid) - // _____ - // rb_stb _______________| |____ (Valid) - // __________________________ - // rb_stb (Valid if readback data is a constant) - // _____ - // rb_stb ___| |________________ (Invalid / ignored, same cycle as set_stb) - // - localparam [7:0] SR_TEST_REG_0 = SR_USER_REG_BASE; - localparam [7:0] SR_TEST_REG_1 = SR_USER_REG_BASE + 8'd1; - - wire [31:0] test_reg_0; - setting_reg #( - .my_addr(SR_TEST_REG_0), .awidth(8), .width(32)) - sr_test_reg_0 ( - .clk(ce_clk), .rst(ce_rst), - .strobe(set_stb), .addr(set_addr), .in(set_data), .out(test_reg_0), .changed()); - - wire [31:0] test_reg_1; - setting_reg #( - .my_addr(SR_TEST_REG_1), .awidth(8), .width(32)) - sr_test_reg_1 ( - .clk(ce_clk), .rst(ce_rst), - .strobe(set_stb), .addr(set_addr), .in(set_data), .out(test_reg_1), .changed()); - - // Readback registers - // rb_stb set to 1'b1 on NoC Shell - always @(posedge ce_clk) begin - case(rb_addr) - 8'd0 : rb_data <= {32'd0, test_reg_0}; - 8'd1 : rb_data <= {32'd0, test_reg_1}; - default : rb_data <= 64'h0BADC0DE0BADC0DE; - endcase - end - - /* Simple Loopback */ - assign m_axis_data_tready = s_axis_data_tready; - assign s_axis_data_tvalid = m_axis_data_tvalid; - assign s_axis_data_tlast = m_axis_data_tlast; - assign s_axis_data_tdata = m_axis_data_tdata; - -endmodule diff --git a/rfnoc/testbenches/CMakeLists.txt b/rfnoc/testbenches/CMakeLists.txt index 09d1f83..97f934d 100644 --- a/rfnoc/testbenches/CMakeLists.txt +++ b/rfnoc/testbenches/CMakeLists.txt @@ -1,2 +1 @@ -add_subdirectory(noc_block_chanmux_tb) add_subdirectory(noc_block_channelizer_tb) diff --git a/rfnoc/testbenches/noc_block_chanmux_tb/CMakeLists.txt b/rfnoc/testbenches/noc_block_chanmux_tb/CMakeLists.txt deleted file mode 100644 index 8b13789..0000000 --- a/rfnoc/testbenches/noc_block_chanmux_tb/CMakeLists.txt +++ /dev/null @@ -1 +0,0 @@ - diff --git a/rfnoc/testbenches/noc_block_chanmux_tb/Makefile b/rfnoc/testbenches/noc_block_chanmux_tb/Makefile deleted file mode 100644 index 4c980ea..0000000 --- a/rfnoc/testbenches/noc_block_chanmux_tb/Makefile +++ /dev/null @@ -1,34 +0,0 @@ - - -# Copyright 2016 Ettus Research - - -#------------------------------------------------- -# Top-of-Makefile -#------------------------------------------------- -# Define BASE_DIR to point to the "top" dir -BASE_DIR = $(FPGA_TOP_DIR)/usrp3/top -# Include viv_sim_preample after defining BASE_DIR -include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak - -#------------------------------------------------- -# Testbench Specific -#------------------------------------------------- -# Define only one toplevel module -SIM_TOP = noc_block_chanmux_tb - -# Add test bench, user design under test, and -# additional user created files -SIM_SRCS = \ -$(abspath noc_block_chanmux_tb.sv) \ -$(abspath ../../fpga-src/noc_block_chanmux.v) - -MODELSIM_USER_DO = - -#------------------------------------------------- -# Bottom-of-Makefile -#------------------------------------------------- -# Include all simulator specific makefiles here -# Each should define a unique target to simulate -# e.g. xsim, vsim, etc and a common "clean" target -include $(BASE_DIR)/../tools/make/viv_simulator.mak diff --git a/rfnoc/testbenches/noc_block_chanmux_tb/noc_block_chanmux_tb.sv b/rfnoc/testbenches/noc_block_chanmux_tb/noc_block_chanmux_tb.sv deleted file mode 100644 index 3e8ea4c..0000000 --- a/rfnoc/testbenches/noc_block_chanmux_tb/noc_block_chanmux_tb.sv +++ /dev/null @@ -1,100 +0,0 @@ -`timescale 1ns/1ps -`define NS_PER_TICK 1 -`define NUM_TEST_CASES 5 - -`include "sim_exec_report.vh" -`include "sim_clks_rsts.vh" -`include "sim_rfnoc_lib.svh" - -module noc_block_chanmux_tb(); - `TEST_BENCH_INIT("noc_block_chanmux",`NUM_TEST_CASES,`NS_PER_TICK); - localparam BUS_CLK_PERIOD = $ceil(1e9/166.67e6); - localparam CE_CLK_PERIOD = $ceil(1e9/200e6); - localparam NUM_CE = 1; // Number of Computation Engines / User RFNoC blocks to simulate - localparam NUM_STREAMS = 1; // Number of test bench streams - `RFNOC_SIM_INIT(NUM_CE, NUM_STREAMS, BUS_CLK_PERIOD, CE_CLK_PERIOD); - `RFNOC_ADD_BLOCK(noc_block_chanmux, 0); - - localparam SPP = 16; // Samples per packet - - /******************************************************** - ** Verification - ********************************************************/ - initial begin : tb_main - string s; - logic [31:0] random_word; - logic [63:0] readback; - - /******************************************************** - ** Test 1 -- Reset - ********************************************************/ - `TEST_CASE_START("Wait for Reset"); - while (bus_rst) @(posedge bus_clk); - while (ce_rst) @(posedge ce_clk); - `TEST_CASE_DONE(~bus_rst & ~ce_rst); - - /******************************************************** - ** Test 2 -- Check for correct NoC IDs - ********************************************************/ - `TEST_CASE_START("Check NoC ID"); - // Read NOC IDs - tb_streamer.read_reg(sid_noc_block_chanmux, RB_NOC_ID, readback); - $display("Read CHANMUX NOC ID: %16x", readback); - `ASSERT_ERROR(readback == noc_block_chanmux.NOC_ID, "Incorrect NOC ID"); - `TEST_CASE_DONE(1); - - /******************************************************** - ** Test 3 -- Connect RFNoC blocks - ********************************************************/ - `TEST_CASE_START("Connect RFNoC blocks"); - `RFNOC_CONNECT(noc_block_tb,noc_block_chanmux,SC16,SPP); - `RFNOC_CONNECT(noc_block_chanmux,noc_block_tb,SC16,SPP); - `TEST_CASE_DONE(1); - - /******************************************************** - ** Test 4 -- Write / readback user registers - ********************************************************/ - `TEST_CASE_START("Write / readback user registers"); - random_word = $random(); - tb_streamer.write_user_reg(sid_noc_block_chanmux, noc_block_chanmux.SR_TEST_REG_0, random_word); - tb_streamer.read_user_reg(sid_noc_block_chanmux, 0, readback); - $sformat(s, "User register 0 incorrect readback! Expected: %0d, Actual %0d", readback[31:0], random_word); - `ASSERT_ERROR(readback[31:0] == random_word, s); - random_word = $random(); - tb_streamer.write_user_reg(sid_noc_block_chanmux, noc_block_chanmux.SR_TEST_REG_1, random_word); - tb_streamer.read_user_reg(sid_noc_block_chanmux, 1, readback); - $sformat(s, "User register 1 incorrect readback! Expected: %0d, Actual %0d", readback[31:0], random_word); - `ASSERT_ERROR(readback[31:0] == random_word, s); - `TEST_CASE_DONE(1); - - /******************************************************** - ** Test 5 -- Test sequence - ********************************************************/ - // chanmux's user code is a loopback, so we should receive - // back exactly what we send - `TEST_CASE_START("Test sequence"); - fork - begin - cvita_payload_t send_payload; - for (int i = 0; i < SPP/2; i++) begin - send_payload.push_back(64'(i)); - end - tb_streamer.send(send_payload); - end - begin - cvita_payload_t recv_payload; - cvita_metadata_t md; - logic [63:0] expected_value; - tb_streamer.recv(recv_payload,md); - for (int i = 0; i < SPP/2; i++) begin - expected_value = i; - $sformat(s, "Incorrect value received! Expected: %0d, Received: %0d", expected_value, recv_payload[i]); - `ASSERT_ERROR(recv_payload[i] == expected_value, s); - end - end - join - `TEST_CASE_DONE(1); - `TEST_BENCH_DONE; - - end -endmodule From 6e321198770c36851750a3356eb44498ebb7b329 Mon Sep 17 00:00:00 2001 From: Nicolas Cuervo Date: Wed, 14 Mar 2018 23:43:36 +0100 Subject: [PATCH 3/5] fpga-src: comply with verilog code guidelines --- rfnoc/fpga-src/channelizer_top.v | 283 +++++------ rfnoc/fpga-src/circ_buffer.v | 272 +++++------ rfnoc/fpga-src/count_cycle_iw36_cw11.v | 60 +-- rfnoc/fpga-src/count_items_iw36_cw11.v | 87 ++-- rfnoc/fpga-src/exp_shifter.v | 426 +++++++++-------- rfnoc/fpga-src/input_buffer.v | 264 +++++------ rfnoc/fpga-src/noc_block_channelizer.v | 87 ++-- rfnoc/fpga-src/pfb_2x.v | 622 +++++++++++++------------ 8 files changed, 1057 insertions(+), 1044 deletions(-) diff --git a/rfnoc/fpga-src/channelizer_top.v b/rfnoc/fpga-src/channelizer_top.v index 10b6c59..c70f499 100644 --- a/rfnoc/fpga-src/channelizer_top.v +++ b/rfnoc/fpga-src/channelizer_top.v @@ -1,32 +1,38 @@ -/*****************************************************************************/ +// +// Copyright 2016-2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: channelizer_top +// Description: +// // Implements the M/2 Channelizer as specified in the // "A Versatile Multichannel Filter Bank with Multiple Channel Bandwidths" paper. -/*****************************************************************************/ module channelizer_top ( - input sync_reset, - input ce_clk, + input sync_reset, + input ce_clk, - input [31:0] s_axis_reload_tdata, - input s_axis_reload_tvalid, - input s_axis_reload_tlast, - output s_axis_reload_tready, + input [31:0] s_axis_reload_tdata, + input s_axis_reload_tvalid, + input s_axis_reload_tlast, + output s_axis_reload_tready, - // currently only supporting up to 512 bins. - input [9:0] fft_size, + // currently only supporting up to 512 bins. + input [9:0] fft_size, - input [31:0] s_axis_tdata, - input s_axis_tvalid, - output s_axis_tready, - output eob_tag, + input [31:0] s_axis_tdata, + input s_axis_tvalid, + output s_axis_tready, + output eob_tag, - output [15:0] m_axis_tuser, - output [31:0] m_axis_tdata, - output m_axis_tvalid, - output m_axis_tlast, - input m_axis_tready + output [15:0] m_axis_tuser, + output [31:0] m_axis_tdata, + output m_axis_tvalid, + output m_axis_tlast, + input m_axis_tready ); @@ -119,24 +125,24 @@ assign s_axis_tready = hb_m_tready; // !axis_prog_full & ; // hb_m_tready & ; //----------------------------------------------- always @(posedge ce_clk) begin - async_reset <= !(sync_reset | reset_int); - async_reset_d1 <= async_reset; + async_reset <= !(sync_reset | reset_int); + async_reset_d1 <= async_reset; end // ensures that reset pulse is wide enough for all blocks. always @* begin - next_reset_cnt = reset_cnt; - if (fft_size_s != fft_size) begin - next_reset_cnt = 5'd04; - end else if (reset_cnt != 0) begin - next_reset_cnt = reset_cnt - 1; - end - if (reset_cnt != 0) begin - next_reset_int = 1'b1; - end else begin - next_reset_int = 1'b0; - end + next_reset_cnt = reset_cnt; + if (fft_size_s != fft_size) begin + next_reset_cnt = 5'd04; + end else if (reset_cnt != 0) begin + next_reset_cnt = reset_cnt - 1; + end + if (reset_cnt != 0) begin + next_reset_int = 1'b1; + end else begin + next_reset_int = 1'b0; + end end // config process -- responsible for configuring the fft size the xfft_stream_var. Note that the @@ -144,64 +150,64 @@ end // adjusted accordingly. always @* begin - next_fft_config_tvalid = fft_config_tvalid; - next_config_state = config_state; - next_nfft = nfft; - case (config_state) - S_CONFIG: - begin - next_fft_config_tvalid = 1'b1; - if (fft_config_tready == 1'b1 && fft_config_tvalid == 1'b1) begin - next_config_state = S_IDLE; - end - if (fft_size == 10'd08) begin - next_nfft = 5'b00011; - end else if (fft_size == 10'd16) begin - next_nfft = 5'b00100; - end else if (fft_size == 10'd32) begin - next_nfft = 5'b00101; - end else if (fft_size == 10'd64) begin - next_nfft = 5'b00110; - end else if (fft_size == 10'd128) begin - next_nfft = 5'b00111; - end else if (fft_size == 10'd256) begin - next_nfft = 5'b01000; - end else if (fft_size == 10'd512) begin - next_nfft = 5'b01001; - end else begin - next_nfft = 5'b01000; - end - - end - S_IDLE: - begin - if (async_reset == 1'b1 && async_reset_d1 == 1'b0) begin - next_config_state = S_CONFIG; - end else begin - next_config_state = S_IDLE; - end - next_fft_config_tvalid = 1'b0; - end - endcase + next_fft_config_tvalid = fft_config_tvalid; + next_config_state = config_state; + next_nfft = nfft; + case (config_state) + S_CONFIG: + begin + next_fft_config_tvalid = 1'b1; + if (fft_config_tready == 1'b1 && fft_config_tvalid == 1'b1) begin + next_config_state = S_IDLE; + end + if (fft_size == 10'd08) begin + next_nfft = 5'b00011; + end else if (fft_size == 10'd16) begin + next_nfft = 5'b00100; + end else if (fft_size == 10'd32) begin + next_nfft = 5'b00101; + end else if (fft_size == 10'd64) begin + next_nfft = 5'b00110; + end else if (fft_size == 10'd128) begin + next_nfft = 5'b00111; + end else if (fft_size == 10'd256) begin + next_nfft = 5'b01000; + end else if (fft_size == 10'd512) begin + next_nfft = 5'b01001; + end else begin + next_nfft = 5'b01000; + end + + end + S_IDLE: + begin + if (async_reset == 1'b1 && async_reset_d1 == 1'b0) begin + next_config_state = S_CONFIG; + end else begin + next_config_state = S_IDLE; + end + next_fft_config_tvalid = 1'b0; + end + endcase end // standard reset and clock process. always @(posedge ce_clk, posedge sync_reset) begin if (sync_reset == 1'b1) begin - config_state <= S_IDLE; - fft_config_tvalid <= 1'b0; - nfft <= 5'b00111; // default to 128 - fft_size_s <= 10'd128; - reset_cnt <= 5'd31; - reset_int <= 1'b1; + config_state <= S_IDLE; + fft_config_tvalid <= 1'b0; + nfft <= 5'b00111; // default to 128 + fft_size_s <= 10'd128; + reset_cnt <= 5'd31; + reset_int <= 1'b1; end else begin - config_state <= next_config_state; - fft_config_tvalid <= next_fft_config_tvalid; - nfft <= next_nfft; - fft_size_s <= fft_size; - reset_cnt <= next_reset_cnt; - reset_int <= next_reset_int; + config_state <= next_config_state; + fft_config_tvalid <= next_fft_config_tvalid; + nfft <= next_nfft; + fft_size_s <= fft_size; + reset_cnt <= next_reset_cnt; + reset_int <= next_reset_int; end end @@ -222,18 +228,18 @@ hb_fil hb_fil ( // Second, it provides a ping-pong buffer interface so that input throttling is mitigated. input_buffer input_buffer ( - .sync_reset(reset_int), - .clk(ce_clk), + .sync_reset(reset_int), + .clk(ce_clk), - .s_tdata(tdata_high_pad), - .s_tvalid(hb_tvalid & !axis_prog_full), //tvalid_high), - .s_tready(in_buff_tready), + .s_tdata(tdata_high_pad), + .s_tvalid(hb_tvalid & !axis_prog_full), //tvalid_high), + .s_tready(in_buff_tready), - .fft_size(fft_size), + .fft_size(fft_size), - .output_sig(buffer_sig), - .phase(buffer_phase), - .valid_out(buffer_valid) //output valid signal. + .output_sig(buffer_sig), + .phase(buffer_phase), + .valid_out(buffer_valid) //output valid signal. ); @@ -246,22 +252,22 @@ input_buffer input_buffer // The nth index is only updated once per revolution of the filter bank. pfb_2x pfb_2x ( - .sync_reset(reset_int), - .clk(ce_clk), - - .phase(buffer_phase), - .fft_size(fft_size), - .input_sig(buffer_sig), - .valid_i(buffer_valid), - - .s_axis_reload_tdata(s_axis_reload_tdata), - .s_axis_reload_tlast(s_axis_reload_tlast), - .s_axis_reload_tvalid(s_axis_reload_tvalid), - .s_axis_reload_tready(s_axis_reload_tready), - - .output_sig(pfb_sig), - .phase_out(pfb_phase), - .valid_out(pfb_valid) //output valid signal. + .sync_reset(reset_int), + .clk(ce_clk), + + .phase(buffer_phase), + .fft_size(fft_size), + .input_sig(buffer_sig), + .valid_i(buffer_valid), + + .s_axis_reload_tdata(s_axis_reload_tdata), + .s_axis_reload_tlast(s_axis_reload_tlast), + .s_axis_reload_tvalid(s_axis_reload_tvalid), + .s_axis_reload_tready(s_axis_reload_tready), + + .output_sig(pfb_sig), + .phase_out(pfb_phase), + .valid_out(pfb_valid) //output valid signal. ); // The circular buffer is similar to the input buffer @@ -269,19 +275,18 @@ pfb_2x pfb_2x // This mitigates the requirement to throttle the input data stream. circ_buffer circ_buffer ( - .sync_reset(reset_int), - .clk(ce_clk), - - .phase(pfb_phase), - .input_sig(pfb_sig), - .valid_i(pfb_valid), + .sync_reset(reset_int), + .clk(ce_clk), - .fft_size(fft_size), + .phase(pfb_phase), + .input_sig(pfb_sig), + .valid_i(pfb_valid), - .m_axis_tdata(circ_buff_tdata), - .m_axis_tvalid(circ_buff_tvalid), - .m_axis_tlast(circ_buff_tlast) + .fft_size(fft_size), + .m_axis_tdata(circ_buff_tdata), + .m_axis_tvalid(circ_buff_tvalid), + .m_axis_tlast(circ_buff_tlast) ); // The primary purpose to this buffer is to provide a throttling condition. The programmed full flag allows @@ -338,27 +343,25 @@ xfft_stream_var xfft_stream_var ( // and flow control logic so that it can directly connected to the rest of the rfnoc // infrastructure. exp_shifter exp_shifter ( - .clk(ce_clk), - .sync_reset(reset_int), - .fft_size(fft_size), - - .s_axis_data_tdata({m_axis_fft_data_tdata[15:0], m_axis_fft_data_tdata[31:16]}), - .s_axis_data_tuser(m_axis_fft_data_tuser), - .s_axis_data_tvalid(m_axis_fft_data_tvalid), - .s_axis_data_tready(m_axis_fft_data_tready), - .s_axis_data_tlast(m_axis_fft_data_tlast), - - .s_axis_status_tdata(m_axis_fft_status_tdata), - .s_axis_status_tvalid(m_axis_fft_status_tvalid), - .s_axis_status_tready(m_axis_fft_status_tready), - .eob_tag(eob_tag), - - .m_axis_tdata(m_axis_tdata), - .m_axis_tuser(m_axis_tuser), - .m_axis_tvalid(m_axis_tvalid), - .m_axis_tlast(m_axis_tlast), - .m_axis_tready(m_axis_tready) + .clk(ce_clk), + .sync_reset(reset_int), + .fft_size(fft_size), + + .s_axis_data_tdata({m_axis_fft_data_tdata[15:0], m_axis_fft_data_tdata[31:16]}), + .s_axis_data_tuser(m_axis_fft_data_tuser), + .s_axis_data_tvalid(m_axis_fft_data_tvalid), + .s_axis_data_tready(m_axis_fft_data_tready), + .s_axis_data_tlast(m_axis_fft_data_tlast), + + .s_axis_status_tdata(m_axis_fft_status_tdata), + .s_axis_status_tvalid(m_axis_fft_status_tvalid), + .s_axis_status_tready(m_axis_fft_status_tready), + .eob_tag(eob_tag), + + .m_axis_tdata(m_axis_tdata), + .m_axis_tuser(m_axis_tuser), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tlast(m_axis_tlast), + .m_axis_tready(m_axis_tready) ); - - endmodule diff --git a/rfnoc/fpga-src/circ_buffer.v b/rfnoc/fpga-src/circ_buffer.v index 54e4fcd..7499ee4 100644 --- a/rfnoc/fpga-src/circ_buffer.v +++ b/rfnoc/fpga-src/circ_buffer.v @@ -1,24 +1,28 @@ -/*****************************************************************************/ +// +// Copyright 2016-2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: circ_buffer +// Description: // The circular buffer implements the circular shifting functionality as // specified in "A Versatile Multichannel Filter Bank with Multiple Channel Bandwidths" paper. // It is implemented using multiple sample memores that allow the block to ping-pong between different memories. // This mitigates the requirement to throttle the input data stream. -// -/*****************************************************************************/ module circ_buffer ( - input sync_reset, - input clk, + input sync_reset, + input clk, - input [8:0] phase, - input [9:0] fft_size, - input [35:0] input_sig, - input valid_i, + input [8:0] phase, + input [9:0] fft_size, + input [35:0] input_sig, + input valid_i, - output [35:0] m_axis_tdata, - output m_axis_tvalid, - output m_axis_tlast + output [35:0] m_axis_tdata, + output m_axis_tvalid, + output m_axis_tlast ); reg mux_switch, next_mux_switch; @@ -38,7 +42,7 @@ reg state, next_state; reg [3:0] rd_en_d; reg [3:0] rd_side_d; -// reg rd_valid, next_rd_valid; + // used to determine the current buffer being read from. reg rd_side, next_rd_side; @@ -82,35 +86,35 @@ assign half_cnt = fft_size[9:1]; // clock and reset process always @(posedge clk, posedge sync_reset) begin - if (sync_reset == 1'b1) begin - mux_switch <= 1'b0; - valid_d <= 0; - tlast <= 1'b0; - rd_en <= 1'b0; - data <= 0; - rd_side <= 1'b0; - rd_en_d <= 0; - state <= S_IDLE; - tvalid <= 1'b0; - write_end <= 1'b0; - last_side <= 1'b0; - rd_cnt_val <= 0; - raddr <= 0; - end else begin - mux_switch <= next_mux_switch; - valid_d <= {valid_d[6:0], valid_i}; - tlast <= next_tlast; - rd_en <= next_rd_en; - data <= next_data; - rd_side <= next_rd_side; - rd_en_d <= {rd_en_d[2:0], rd_en}; - state <= next_state; - tvalid <= next_tvalid; - write_end <= next_write_end; - last_side <= next_last_side; - rd_cnt_val <= next_rd_cnt_val; - raddr <= next_raddr; - end + if (sync_reset == 1'b1) begin + mux_switch <= 1'b0; + valid_d <= 0; + tlast <= 1'b0; + rd_en <= 1'b0; + data <= 0; + rd_side <= 1'b0; + rd_en_d <= 0; + state <= S_IDLE; + tvalid <= 1'b0; + write_end <= 1'b0; + last_side <= 1'b0; + rd_cnt_val <= 0; + raddr <= 0; + end else begin + mux_switch <= next_mux_switch; + valid_d <= {valid_d[6:0], valid_i}; + tlast <= next_tlast; + rd_en <= next_rd_en; + data <= next_data; + rd_side <= next_rd_side; + rd_en_d <= {rd_en_d[2:0], rd_en}; + state <= next_state; + tvalid <= next_tvalid; + write_end <= next_write_end; + last_side <= next_last_side; + rd_cnt_val <= next_rd_cnt_val; + raddr <= next_raddr; + end end @@ -118,119 +122,118 @@ end integer i; always @(posedge clk) begin - we_0 <= next_we_0; - we_1 <= next_we_1; - - phase_end <= fft_size - 10'd1; - output_s <= next_output_s; - phase_d[0] <= phase; - for (i=1; i<5; i=i+1) begin - phase_d[i] <= phase_d[i-1]; - end - input_d[0] <= input_sig; - for (i=1; i<5; i=i+1) begin - input_d[i] <= input_d[i-1]; - end - - rd_side_d <= {rd_side_d[2:0], rd_side}; - rd_cnt_d[0] <= rd_cnt_val; - for (i=1;i<4;i=i+1) begin - rd_cnt_d[i] <= rd_cnt_d[i-1]; - end + we_0 <= next_we_0; + we_1 <= next_we_1; + + phase_end <= fft_size - 10'd1; + output_s <= next_output_s; + phase_d[0] <= phase; + for (i=1; i<5; i=i+1) begin + phase_d[i] <= phase_d[i-1]; + end + input_d[0] <= input_sig; + for (i=1; i<5; i=i+1) begin + input_d[i] <= input_d[i-1]; + end + + rd_side_d <= {rd_side_d[2:0], rd_side}; + rd_cnt_d[0] <= rd_cnt_val; + for (i=1;i<4;i=i+1) begin + rd_cnt_d[i] <= rd_cnt_d[i-1]; + end end // write process. Keeps track of current buffer being written. always @* begin - next_we_0 = 1'b0; - next_we_1 = 1'b0; - if ((phase_d[3] == phase_end_s) && (valid_d[3] == 1'b1)) begin - next_mux_switch = !mux_switch; - end else begin - next_mux_switch = mux_switch; - end - if (valid_d[3] == 1'b1) begin - next_we_0 = !mux_switch; - next_we_1 = mux_switch; - end - + next_we_0 = 1'b0; + next_we_1 = 1'b0; + if ((phase_d[3] == phase_end_s) && (valid_d[3] == 1'b1)) begin + next_mux_switch = !mux_switch; + end else begin + next_mux_switch = mux_switch; + end + if (valid_d[3] == 1'b1) begin + next_we_0 = !mux_switch; + next_we_1 = mux_switch; + end end // read process. Controls the read pointers of the RAMs. Pushes data out of the circular shift_val // buffers always @* begin - next_state = state; - next_rd_en = rd_en; - next_rd_side = rd_side; - next_write_end = write_end; - next_last_side = last_side; - next_rd_cnt_val = rd_cnt_val; - case (state) - S_IDLE: - begin - // currently writing the last value. - if (write_end_logic == 1'b1) begin // phase_d[1] == 8'd255 && (we_0 == 1'b1 || we_1 == 1'b1)) begin - next_rd_en = 1'b1; - next_state = S_READ; - next_write_end = 1'b0; - next_rd_cnt_val = 0; - next_rd_side = mux_switch; - end + next_state = state; + next_rd_en = rd_en; + next_rd_side = rd_side; + next_write_end = write_end; + next_last_side = last_side; + next_rd_cnt_val = rd_cnt_val; + case (state) + S_IDLE: + begin + // currently writing the last value. + if (write_end_logic == 1'b1) begin // phase_d[1] == 8'd255 && (we_0 == 1'b1 || we_1 == 1'b1)) begin + next_rd_en = 1'b1; + next_state = S_READ; + next_write_end = 1'b0; + next_rd_cnt_val = 0; + next_rd_side = mux_switch; + end + end + S_READ: + begin + if (rd_cnt_val == phase_end) begin + if (write_end == 1'b1 || write_end_logic == 1'b1) begin + next_rd_en = 1'b1; + next_rd_cnt_val = 0; + next_state = S_READ; + next_write_end = 1'b0; + if (write_end_logic == 1'b1) begin + next_rd_side = mux_switch; + end else begin + next_rd_side = last_side; + end + end else begin + next_state = S_IDLE; + next_rd_en = 1'b0; end - S_READ: - begin - if (rd_cnt_val == phase_end) begin - if (write_end == 1'b1 || write_end_logic == 1'b1) begin - next_rd_en = 1'b1; - next_rd_cnt_val = 0; - next_state = S_READ; - next_write_end = 1'b0; - if (write_end_logic == 1'b1) begin - next_rd_side = mux_switch; - end else begin - next_rd_side = last_side; - end - end else begin - next_state = S_IDLE; - next_rd_en = 1'b0; - end - end else begin - next_rd_cnt_val = rd_cnt_val + 1; - if (write_end_logic == 1'b1) begin - next_write_end = 1'b1; - next_last_side = mux_switch; - end - end + end else begin + next_rd_cnt_val = rd_cnt_val + 1; + if (write_end_logic == 1'b1) begin + next_write_end = 1'b1; + next_last_side = mux_switch; end - endcase + end + end + endcase end // output pipelining always @* begin - // next_rd_valid = 1'b0; - next_data = data; - next_tlast = 1'b0; - next_tvalid = rd_en_d[3]; // & rd_en_d[6]; - // output of dual port ram is valid. - if (rd_en_d[3] == 1'b1) begin - // reading from top setp of buffers - if (rd_side_d[3] == 1'b0) begin - next_data = ram0; - end else begin - next_data = ram1; - end - if (rd_cnt_d[3] == phase_end) begin - next_tlast = 1'b1; - end - end - if (rd_side == 1'b1) begin - next_raddr = (half_cnt + rd_cnt_val) & phase_end_s; + // next_rd_valid = 1'b0; + next_data = data; + next_tlast = 1'b0; + next_tvalid = rd_en_d[3]; // & rd_en_d[6]; + // output of dual port ram is valid. + if (rd_en_d[3] == 1'b1) begin + // reading from top setp of buffers + if (rd_side_d[3] == 1'b0) begin + next_data = ram0; end else begin - next_raddr = rd_cnt_val; + next_data = ram1; end + if (rd_cnt_d[3] == phase_end) begin + next_tlast = 1'b1; + end + end + if (rd_side == 1'b1) begin + next_raddr = (half_cnt + rd_cnt_val) & phase_end_s; + end else begin + next_raddr = rd_cnt_val; + end end // Ping-pong memories. @@ -256,5 +259,4 @@ circ_buff_ram circ_buff_1 ( .doutb(ram1) // output wire [35 : 0] doutb ); - endmodule diff --git a/rfnoc/fpga-src/count_cycle_iw36_cw11.v b/rfnoc/fpga-src/count_cycle_iw36_cw11.v index 469b3c8..24109d0 100644 --- a/rfnoc/fpga-src/count_cycle_iw36_cw11.v +++ b/rfnoc/fpga-src/count_cycle_iw36_cw11.v @@ -1,21 +1,25 @@ -/*****************************************************************************/ +// +// Copyright 2016-2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: count_cycle_iw36_cw11 +// Description: // Implement simple count / data alignment logic while optimizing pipelining. // Used inside the input_buffer module to appropriately segment sample blocks. -// -/*****************************************************************************/ module count_cycle_iw36_cw11 ( - input sync_reset, - input clk, + input sync_reset, + input clk, - input [35:0] data_i, - input [10:0] high_cnt, - input valid_i, + input [35:0] data_i, + input [10:0] high_cnt, + input valid_i, - output [35:0] data_out, - output [10:0] count, - output valid_out + output [35:0] data_out, + output [10:0] count, + output valid_out ); reg reset_cnt, next_reset_cnt; @@ -35,40 +39,37 @@ assign count = count_value; always @(posedge clk, posedge sync_reset) begin if (sync_reset == 1'b1) begin - reset_cnt <= 1'b1; + reset_cnt <= 1'b1; end else begin - reset_cnt <= next_reset_cnt; + reset_cnt <= next_reset_cnt; end end - // delay process always @(posedge clk) begin - valid_d1 <= valid_i; - data_d1 <= data_i; - reset_flag1 <= high_cnt - 11'd1; - reset_flag2 <= high_cnt - 11'd2; + valid_d1 <= valid_i; + data_d1 <= data_i; + reset_flag1 <= high_cnt - 11'd1; + reset_flag2 <= high_cnt - 11'd2; end - // write process. always @* begin - if (reset_cnt == 1'b1) begin - next_reset_cnt = 1'b0; - end else if (valid_i == 1'b1) begin - if ((count_value == reset_flag1 && valid_d1 == 1'b0) || (count_value == reset_flag2 && valid_d1 == 1'b1)) begin - next_reset_cnt = 1'b1; - end else begin - next_reset_cnt = 1'b0; - end + if (reset_cnt == 1'b1) begin + next_reset_cnt = 1'b0; + end else if (valid_i == 1'b1) begin + if ((count_value == reset_flag1 && valid_d1 == 1'b0) || (count_value == reset_flag2 && valid_d1 == 1'b1)) begin + next_reset_cnt = 1'b1; end else begin - next_reset_cnt = 1'b0; + next_reset_cnt = 1'b0; end + end else begin + next_reset_cnt = 1'b0; + end end - count_items_iw36_cw11 count_items ( .sync_reset(sync_reset), @@ -81,5 +82,4 @@ count_items_iw36_cw11 count_items .data_o(count_data) ); - endmodule diff --git a/rfnoc/fpga-src/count_items_iw36_cw11.v b/rfnoc/fpga-src/count_items_iw36_cw11.v index 3387176..5f9e64c 100644 --- a/rfnoc/fpga-src/count_items_iw36_cw11.v +++ b/rfnoc/fpga-src/count_items_iw36_cw11.v @@ -1,3 +1,11 @@ +// +// Copyright 2016-2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: count_items_iw36_cw11 +// Description: +// Simple module to count items used in count_cycle_iw36_cw11 module count_items_iw36_cw11 ( input sync_reset, @@ -10,7 +18,6 @@ module count_items_iw36_cw11 output [35:0] data_o ); - reg [10:0] cnt, next_cnt; reg [10:0] cnt_d1, next_cnt_d1; @@ -30,53 +37,51 @@ assign reset_cnt_s = (first_flag == 1'b1 && valid_i == 1'b1) ? 1'b1 : reset_cnt // do a reset always @(posedge clk, posedge sync_reset) begin - if (sync_reset == 1'b1) begin - init_cnt <= 2'b01; - count_valid <= 1'b0; - first_flag <= 1'b1; - out_d0 <= 0; - out_d1 <= 0; - cnt <= 0; - cnt_d1 <= 0; - end else begin - out_d0 <= next_out_d0; - out_d1 <= next_out_d1; - init_cnt <= next_init_cnt; - first_flag <= next_first_flag; - count_valid <= next_count_valid; - cnt <= next_cnt; - cnt_d1 <= next_cnt_d1; - end + if (sync_reset == 1'b1) begin + init_cnt <= 2'b01; + count_valid <= 1'b0; + first_flag <= 1'b1; + out_d0 <= 0; + out_d1 <= 0; + cnt <= 0; + cnt_d1 <= 0; + end else begin + out_d0 <= next_out_d0; + out_d1 <= next_out_d1; + init_cnt <= next_init_cnt; + first_flag <= next_first_flag; + count_valid <= next_count_valid; + cnt <= next_cnt; + cnt_d1 <= next_cnt_d1; + end end always @* begin - next_out_d0 = out_d0; - next_out_d1 = out_d1; - next_init_cnt = init_cnt; - next_count_valid = 1'b0; - next_first_flag = first_flag; + next_out_d0 = out_d0; + next_out_d1 = out_d1; + next_init_cnt = init_cnt; + next_count_valid = 1'b0; + next_first_flag = first_flag; next_cnt = cnt; next_cnt_d1 = cnt_d1; - if (valid_i == 1'b1) begin - next_out_d0 = data_i; - next_first_flag = 1'b0; - next_out_d1 = out_d0; - next_cnt_d1 = cnt; - if (init_cnt != 0) begin - next_init_cnt = init_cnt - 1; - end - if (reset_cnt_s == 1'b1) begin - next_cnt = 11'd0; - end else begin - next_cnt = cnt + 1; - end - - if (init_cnt == 0 && valid_i == 1'b1) begin - next_count_valid = 1'b1; - end + if (valid_i == 1'b1) begin + next_out_d0 = data_i; + next_first_flag = 1'b0; + next_out_d1 = out_d0; + next_cnt_d1 = cnt; + if (init_cnt != 0) begin + next_init_cnt = init_cnt - 1; + end + if (reset_cnt_s == 1'b1) begin + next_cnt = 11'd0; + end else begin + next_cnt = cnt + 1; + end + if (init_cnt == 0 && valid_i == 1'b1) begin + next_count_valid = 1'b1; + end end end - endmodule diff --git a/rfnoc/fpga-src/exp_shifter.v b/rfnoc/fpga-src/exp_shifter.v index e697664..3806956 100644 --- a/rfnoc/fpga-src/exp_shifter.v +++ b/rfnoc/fpga-src/exp_shifter.v @@ -1,4 +1,10 @@ -/*****************************************************************************/ +// +// Copyright 2016-2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: exp_shifter +// Description: // // Since the fft is block floating point the apparent signal amplitude can be shifted // in consecutive fft blocks. The Exponent shifter, exp_shifter, implements a simple @@ -6,36 +12,33 @@ // the amplitude shifts caused by the fft module. The module also provides buffering // and flow control logic so that it can directly connected to the rest of the rfnoc // infrastructure. -/*****************************************************************************/ - module exp_shifter ( - // input [4:0] min_shift_val, - input clk, - input sync_reset, - - input [31:0] s_axis_data_tdata, - input [23:0] s_axis_data_tuser, - input s_axis_data_tvalid, - output s_axis_data_tready, - input [9:0] fft_size, - - input s_axis_data_tlast, - input [7:0] s_axis_status_tdata, - input s_axis_status_tvalid, - output s_axis_status_tready, - - output [31:0] m_axis_tdata, - output [23:0] m_axis_tuser, - output m_axis_tvalid, - output eob_tag, - output m_axis_tlast, - input m_axis_tready // ready out + // input [4:0] min_shift_val, + input clk, + input sync_reset, + + input [31:0] s_axis_data_tdata, + input [23:0] s_axis_data_tuser, + input s_axis_data_tvalid, + output s_axis_data_tready, + input [9:0] fft_size, + + input s_axis_data_tlast, + input [7:0] s_axis_status_tdata, + input s_axis_status_tvalid, + output s_axis_status_tready, + + output [31:0] m_axis_tdata, + output [23:0] m_axis_tuser, + output m_axis_tvalid, + output eob_tag, + output m_axis_tlast, + input m_axis_tready // ready out ); // status register BLK_EXP[4:0] - reg signed [5:0] sub_out; reg signed [5:0] next_sub_out; wire filter_tready; @@ -57,11 +60,9 @@ reg [15:0] filter_tdata_d0; wire [10:0] axis_data_count; // output wire [10 : 0] axis_data_count reg [15:0] next_filter_tdata_d0; - reg [15:0] filter_ref, next_filter_ref; reg [7:0] samp_cnt, next_samp_cnt; - reg [7:0] samp_cnt_out, next_samp_cnt_out; wire [31:0] p_ival, p_qval; @@ -79,7 +80,6 @@ wire s_axis_data_tready_s; wire fifo_tready; wire axis_prog_full; -// wire ce; // channels are stored in 12:8 vector of the tuser input assign s_axis_data_tready_s = !axis_prog_full & filter_tready; @@ -154,19 +154,19 @@ exp_shifter_fifo exp_shifter_fifo ( always @(posedge clk, posedge sync_reset) begin if (sync_reset == 1'b1) begin - chan_0 <= 1'b0; - filter_tdata_d0 <= 0; - filter_ref <= 0; - sub_out <= 0; - samp_cnt <= 8'd255; - samp_cnt_out <= 8'd255; + chan_0 <= 1'b0; + filter_tdata_d0 <= 0; + filter_ref <= 0; + sub_out <= 0; + samp_cnt <= 8'd255; + samp_cnt_out <= 8'd255; end else begin - chan_0 <= next_chan_0; - filter_tdata_d0 <= next_filter_tdata_d0; - filter_ref <= next_filter_ref; - sub_out <= next_sub_out; - samp_cnt <= next_samp_cnt; - samp_cnt_out <= next_samp_cnt_out; + chan_0 <= next_chan_0; + filter_tdata_d0 <= next_filter_tdata_d0; + filter_ref <= next_filter_ref; + sub_out <= next_sub_out; + samp_cnt <= next_samp_cnt; + samp_cnt_out <= next_samp_cnt_out; end end @@ -175,200 +175,192 @@ end integer i; always @(posedge clk) begin + fft_m2 <= fft_size - 2; + fft_m1 <= fft_size - 1; + tvalid_d[0] <= take_data; + for (i = 1; i < 7; i = i + 1) begin + tvalid_d[i] <= tvalid_d[i-1]; + end + tuser_d[0] <= {s_axis_data_tlast, s_axis_data_tuser[22:0]}; + for (i = 1; i < 7; i = i + 1) begin + tuser_d[i] <= tuser_d[i-1]; + end + tlast_d[0] <= s_axis_data_tlast; + if (samp_cnt == 8'd255 && tvalid_d[0] == 1'b1) begin + tlast_d[1] <= 1'b1; + end else begin + tlast_d[1] <= 1'b0; + end + for (i = 2; i < 7; i = i + 1) begin + tlast_d[i] <= tlast_d[i-1]; + end + tdata_d[0] <= s_axis_data_tdata; + for (i=1; i < 3; i = i + 1) begin + tdata_d[i] <= tdata_d[i-1]; + end + i_val <= next_i_val; + q_val <= next_q_val; + shift_val <= sub_out - $signed(6'd3); +end - fft_m2 <= fft_size - 2; - fft_m1 <= fft_size - 1; - tvalid_d[0] <= take_data; - for (i = 1; i < 7; i = i + 1) begin - tvalid_d[i] <= tvalid_d[i-1]; - end - - tuser_d[0] <= {s_axis_data_tlast, s_axis_data_tuser[22:0]}; - for (i = 1; i < 7; i = i + 1) begin - tuser_d[i] <= tuser_d[i-1]; - end - - tlast_d[0] <= s_axis_data_tlast; - if (samp_cnt == 8'd255 && tvalid_d[0] == 1'b1) begin - tlast_d[1] <= 1'b1; +// tready logic. +always @* +begin + next_chan_0 = chan_0; + next_samp_cnt = samp_cnt; + next_samp_cnt_out = samp_cnt_out; + if (s_axis_data_tuser[8:0] == 9'd0 && take_data == 1'b1) begin + next_chan_0 <= 1'b1; + end else begin + next_chan_0 <= 1'b0; + end + + next_filter_tdata_d0 = filter_tdata_d0; + if (filter_tvalid == 1'b1) begin + next_filter_tdata_d0 = filter_tdata; + end + + next_filter_ref = filter_ref; + if (s_axis_data_tuser[8:0] == 9'd0 && take_data == 1'b1) begin + next_filter_ref = filter_tdata_d0; + end + + next_sub_out = sub_out; + if (chan_0 == 1'b1) begin + next_sub_out = $signed(tuser_d[0][20:16]) - $signed(filter_ref[10:6]); + end + + // logic was used as internal debugging signals. + if (take_data) begin + // recovery logic. + if (samp_cnt == 8'd255) begin + next_samp_cnt = 0; + // got off cut. + end else if (mask != fft_m2[7:0] && s_axis_data_tlast == 1'b1) begin + next_samp_cnt = 8'd255; end else begin - tlast_d[1] <= 1'b0; - end - for (i = 2; i < 7; i = i + 1) begin - tlast_d[i] <= tlast_d[i-1]; + next_samp_cnt = samp_cnt + 1; end + end - tdata_d[0] <= s_axis_data_tdata; - for (i=1; i < 3; i = i + 1) begin - tdata_d[i] <= tdata_d[i-1]; + if (m_axis_tvalid_s == 1'b1 && m_axis_tready_s == 1'b1) begin + if (m_axis_tlast_s == 1'b1) begin + next_samp_cnt_out = 0; + end else begin + next_samp_cnt_out = samp_cnt_out + 1; end - - i_val <= next_i_val; - q_val <= next_q_val; - shift_val <= sub_out - $signed(6'd3); - + end end -// tready logic. +// output slicing. Takes the filtered shift value and appropriately grabs the correct slice +// of the output signal. Implemented as a bounded case statement. always @* begin - - next_chan_0 = chan_0; - next_samp_cnt = samp_cnt; - next_samp_cnt_out = samp_cnt_out; - if (s_axis_data_tuser[8:0] == 9'd0 && take_data == 1'b1) begin - next_chan_0 <= 1'b1; - end else begin - next_chan_0 <= 1'b0; + case (shift_val) + 7'd0 : + begin + next_i_val = tdata_d[2][15:0]; + next_q_val = tdata_d[2][31:16]; end - - next_filter_tdata_d0 = filter_tdata_d0; - if (filter_tvalid == 1'b1) begin - next_filter_tdata_d0 = filter_tdata; + 7'd1: + begin + next_i_val = {tdata_d[2][14:0], 1'b0}; + next_q_val = {tdata_d[2][30:16], 1'b0}; end - - next_filter_ref = filter_ref; - if (s_axis_data_tuser[8:0] == 9'd0 && take_data == 1'b1) begin - next_filter_ref = filter_tdata_d0; + 7'd2: + begin + next_i_val = {tdata_d[2][13:0], 2'd0}; + next_q_val = {tdata_d[2][29:16], 2'd0}; end - - next_sub_out = sub_out; - if (chan_0 == 1'b1) begin - next_sub_out = $signed(tuser_d[0][20:16]) - $signed(filter_ref[10:6]); + 7'd3: + begin + next_i_val = {tdata_d[2][12:0], 3'd0}; + next_q_val = {tdata_d[2][28:16], 3'd0}; end - - // logic was used as internal debugging signals. - if (take_data) begin - // recovery logic. - if (samp_cnt == 8'd255) begin - next_samp_cnt = 0; - // got off cut. - end else if (mask != fft_m2[7:0] && s_axis_data_tlast == 1'b1) begin - next_samp_cnt = 8'd255; - end else begin - next_samp_cnt = samp_cnt + 1; - end + 7'd4: + begin + next_i_val = {tdata_d[2][11:0], 4'd0}; + next_q_val = {tdata_d[2][27:16], 4'd0}; end - - if (m_axis_tvalid_s == 1'b1 && m_axis_tready_s == 1'b1) begin - if (m_axis_tlast_s == 1'b1) begin - next_samp_cnt_out = 0; - end else begin - next_samp_cnt_out = samp_cnt_out + 1; - end + 7'd5: + begin + next_i_val = {tdata_d[2][10:0], 5'd0}; + next_q_val = {tdata_d[2][26:16], 5'd0}; end -end + 7'd6: + begin + next_i_val = {tdata_d[2][9:0], 6'd0}; + next_q_val = {tdata_d[2][25:16], 6'd0}; + end + 7'd7: + begin + next_i_val = {tdata_d[2][9:0], 7'd0}; + next_q_val = {tdata_d[2][24:16], 7'd0}; + end + // Maximum scaling gain = 2^7 + -7'd1: + begin + next_i_val = {{1{tdata_d[2][15]}}, tdata_d[2][15:1]}; + next_q_val = {{1{tdata_d[2][31]}}, tdata_d[2][31:17]}; + end + -7'd2: + begin + next_i_val = {{2{tdata_d[2][15]}}, tdata_d[2][15:2]}; + next_q_val = {{2{tdata_d[2][31]}}, tdata_d[2][31:18]}; + end + -7'd3: + begin + next_i_val = {{3{tdata_d[2][15]}}, tdata_d[2][15:3]}; + next_q_val = {{3{tdata_d[2][31]}}, tdata_d[2][31:19]}; + end + -7'd4: + begin + next_i_val = {{4{tdata_d[2][15]}}, tdata_d[2][15:4]}; + next_q_val = {{4{tdata_d[2][31]}}, tdata_d[2][31:20]}; + end + -7'd5: + begin + next_i_val = {{5{tdata_d[2][15]}}, tdata_d[2][15:5]}; + next_q_val = {{5{tdata_d[2][31]}}, tdata_d[2][31:21]}; + end + -7'd6: + begin + next_i_val = {{6{tdata_d[2][15]}}, tdata_d[2][15:6]}; + next_q_val = {{6{tdata_d[2][31]}}, tdata_d[2][31:22]}; + end + -7'd7: + begin + next_i_val = {{7{tdata_d[2][15]}}, tdata_d[2][15:7]}; + next_q_val = {{7{tdata_d[2][31]}}, tdata_d[2][31:23]}; + end + -7'd8: + begin + next_i_val = {{8{tdata_d[2][15]}}, tdata_d[2][15:8]}; + next_q_val = {{8{tdata_d[2][31]}}, tdata_d[2][31:24]}; + end + -7'd9: + begin + next_i_val = {{9{tdata_d[2][15]}}, tdata_d[2][15:9]}; + next_q_val = {{9{tdata_d[2][31]}}, tdata_d[2][31:25]}; + end + -7'd10: + begin + next_i_val = {{10{tdata_d[2][15]}}, tdata_d[2][15:10]}; + next_q_val = {{10{tdata_d[2][31]}}, tdata_d[2][31:26]}; + end -// output slicing. Takes the filtered shift value and appropriately grabs the correct slice -// of the output signal. Implemented as a bounded case statement. -always @* -begin - case (shift_val) - 7'd0 : - begin - next_i_val = tdata_d[2][15:0]; - next_q_val = tdata_d[2][31:16]; - end - 7'd1: - begin - next_i_val = {tdata_d[2][14:0], 1'b0}; - next_q_val = {tdata_d[2][30:16], 1'b0}; - end - 7'd2: - begin - next_i_val = {tdata_d[2][13:0], 2'd0}; - next_q_val = {tdata_d[2][29:16], 2'd0}; - end - 7'd3: - begin - next_i_val = {tdata_d[2][12:0], 3'd0}; - next_q_val = {tdata_d[2][28:16], 3'd0}; - end - 7'd4: - begin - next_i_val = {tdata_d[2][11:0], 4'd0}; - next_q_val = {tdata_d[2][27:16], 4'd0}; - end - 7'd5: - begin - next_i_val = {tdata_d[2][10:0], 5'd0}; - next_q_val = {tdata_d[2][26:16], 5'd0}; - end - 7'd6: - begin - next_i_val = {tdata_d[2][9:0], 6'd0}; - next_q_val = {tdata_d[2][25:16], 6'd0}; - end - 7'd7: - begin - next_i_val = {tdata_d[2][9:0], 7'd0}; - next_q_val = {tdata_d[2][24:16], 7'd0}; - end - // Maximum scaling gain = 2^7 - - -7'd1: - begin - next_i_val = {{1{tdata_d[2][15]}}, tdata_d[2][15:1]}; - next_q_val = {{1{tdata_d[2][31]}}, tdata_d[2][31:17]}; - end - -7'd2: - begin - next_i_val = {{2{tdata_d[2][15]}}, tdata_d[2][15:2]}; - next_q_val = {{2{tdata_d[2][31]}}, tdata_d[2][31:18]}; - end - -7'd3: - begin - next_i_val = {{3{tdata_d[2][15]}}, tdata_d[2][15:3]}; - next_q_val = {{3{tdata_d[2][31]}}, tdata_d[2][31:19]}; - end - -7'd4: - begin - next_i_val = {{4{tdata_d[2][15]}}, tdata_d[2][15:4]}; - next_q_val = {{4{tdata_d[2][31]}}, tdata_d[2][31:20]}; - end - -7'd5: - begin - next_i_val = {{5{tdata_d[2][15]}}, tdata_d[2][15:5]}; - next_q_val = {{5{tdata_d[2][31]}}, tdata_d[2][31:21]}; - end - -7'd6: - begin - next_i_val = {{6{tdata_d[2][15]}}, tdata_d[2][15:6]}; - next_q_val = {{6{tdata_d[2][31]}}, tdata_d[2][31:22]}; - end - -7'd7: - begin - next_i_val = {{7{tdata_d[2][15]}}, tdata_d[2][15:7]}; - next_q_val = {{7{tdata_d[2][31]}}, tdata_d[2][31:23]}; - end - -7'd8: - begin - next_i_val = {{8{tdata_d[2][15]}}, tdata_d[2][15:8]}; - next_q_val = {{8{tdata_d[2][31]}}, tdata_d[2][31:24]}; - end - -7'd9: - begin - next_i_val = {{9{tdata_d[2][15]}}, tdata_d[2][15:9]}; - next_q_val = {{9{tdata_d[2][31]}}, tdata_d[2][31:25]}; - end - -7'd10: - begin - next_i_val = {{10{tdata_d[2][15]}}, tdata_d[2][15:10]}; - next_q_val = {{10{tdata_d[2][31]}}, tdata_d[2][31:26]}; - end - - default : - begin - if (shift_val[6] == 1'b0) begin - next_i_val = {tdata_d[2][9:0], 7'd0}; - next_q_val = {tdata_d[2][24:16], 7'd0}; - end else begin - next_i_val = {{10{tdata_d[2][15]}}, tdata_d[2][15:10]}; - next_q_val = {{10{tdata_d[2][31]}}, tdata_d[2][31:26]}; - end - end - endcase + default : + begin + if (shift_val[6] == 1'b0) begin + next_i_val = {tdata_d[2][9:0], 7'd0}; + next_q_val = {tdata_d[2][24:16], 7'd0}; + end else begin + next_i_val = {{10{tdata_d[2][15]}}, tdata_d[2][15:10]}; + next_q_val = {{10{tdata_d[2][31]}}, tdata_d[2][31:26]}; + end + end + endcase end endmodule diff --git a/rfnoc/fpga-src/input_buffer.v b/rfnoc/fpga-src/input_buffer.v index 56121b8..131dc44 100644 --- a/rfnoc/fpga-src/input_buffer.v +++ b/rfnoc/fpga-src/input_buffer.v @@ -1,25 +1,28 @@ -/*****************************************************************************/ // +// Copyright 2016-2018 Ettus Research, A National Instruments Company // +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: input_buffer +// Description: // The muxing shown provides the capability for the input buffer to be reading one dual port ram while // the other is being written. The fixed counters provide the appropriate addressing for both reading // and writing RAMs. Note that input data rate must be 1/2 the clock rate to maintain unthrottled performance -/*****************************************************************************/ module input_buffer ( - input sync_reset, - input clk, + input sync_reset, + input clk, - input [35:0] s_tdata, - input s_tvalid, - output s_tready, + input [35:0] s_tdata, + input s_tvalid, + output s_tready, - input [9:0] fft_size, + input [9:0] fft_size, - output [35:0] output_sig, - output [8:0] phase, - output valid_out + output [35:0] output_sig, + output [8:0] phase, + output valid_out ); @@ -93,33 +96,33 @@ assign output_sig = data; always @(posedge clk, posedge sync_reset) begin if (sync_reset == 1'b1) begin - we_side <= 1'b0; - rd_side <= 1'b0; - we_0 <= 1'b0; - we_1 <= 1'b0; - state <= S_IDLE; - rd_en <= 1'b0; - rd_en_d <= 0; - data <= 0; - tvalid <= 1'b0; - phase_s <= 0; - read_addr <= 0; - tready <= 1'b1; - write_done <= 1'b0; + we_side <= 1'b0; + rd_side <= 1'b0; + we_0 <= 1'b0; + we_1 <= 1'b0; + state <= S_IDLE; + rd_en <= 1'b0; + rd_en_d <= 0; + data <= 0; + tvalid <= 1'b0; + phase_s <= 0; + read_addr <= 0; + tready <= 1'b1; + write_done <= 1'b0; end else begin - we_side <= next_we_side; - rd_side <= next_rd_side; - we_0 <= next_we_0; - we_1 <= next_we_1; - state <= next_state; - rd_en <= next_rd_en; - rd_en_d <= {rd_en_d[2:0], rd_en}; - data <= next_data; - tvalid <= next_tvalid; - phase_s <= next_phase; - read_addr <= next_read_addr; - tready <= next_tready; - write_done <= next_write_done; + we_side <= next_we_side; + rd_side <= next_rd_side; + we_0 <= next_we_0; + we_1 <= next_we_1; + state <= next_state; + rd_en <= next_rd_en; + rd_en_d <= {rd_en_d[2:0], rd_en}; + data <= next_data; + tvalid <= next_tvalid; + phase_s <= next_phase; + read_addr <= next_read_addr; + tready <= next_tready; + write_done <= next_write_done; end end @@ -128,125 +131,125 @@ end // by the read_window signal. always @(posedge clk) begin - addra <= count_offset; - count_data_d1 <= count_data; - count_data_d2 <= count_data_d1; - count_valid_d1 <= count_valid; - count_value_d1 <= count_value; - count_offset <= roll_over - count_value; - read_addr_d1 <= read_addr; - read_addr_d2 <= read_addr_d1; - read_addr_d3 <= read_addr_d2; - read_addr_d4 <= read_addr_d3; - fft_max <= fft_size - 1; - fft_max_slice <= fft_max[8:0]; - roll_over <= fft_max_slice[8:1]; - rd_side_d <= {rd_side_d[2:0], rd_side}; - roll_over_offset <= roll_over - 2; - roll_over_m1 <= roll_over - 1; - take_data_d1 <= take_data; - fft_max_m3 <= fft_max - 3; - fft_max_m2 <= fft_max - 2; - fft_max_m1 <= fft_max - 1; + addra <= count_offset; + count_data_d1 <= count_data; + count_data_d2 <= count_data_d1; + count_valid_d1 <= count_valid; + count_value_d1 <= count_value; + count_offset <= roll_over - count_value; + read_addr_d1 <= read_addr; + read_addr_d2 <= read_addr_d1; + read_addr_d3 <= read_addr_d2; + read_addr_d4 <= read_addr_d3; + fft_max <= fft_size - 1; + fft_max_slice <= fft_max[8:0]; + roll_over <= fft_max_slice[8:1]; + rd_side_d <= {rd_side_d[2:0], rd_side}; + roll_over_offset <= roll_over - 2; + roll_over_m1 <= roll_over - 1; + take_data_d1 <= take_data; + fft_max_m3 <= fft_max - 3; + fft_max_m2 <= fft_max - 2; + fft_max_m1 <= fft_max - 1; end // write process. Keeps track of current buffer being written. always @* begin - next_we_0 = 1'b0; - next_we_1 = 1'b0; - next_we_side = we_side; - if (count_valid_d1 == 1'b1) begin - if (we_side == 1'b0) begin - next_we_0 = 1'b1; - end else begin - next_we_1 = 1'b1; - end - if (count_offset == 0) begin - next_we_side = ~we_side; - end + next_we_0 = 1'b0; + next_we_1 = 1'b0; + next_we_side = we_side; + if (count_valid_d1 == 1'b1) begin + if (we_side == 1'b0) begin + next_we_0 = 1'b1; + end else begin + next_we_1 = 1'b1; end + if (count_offset == 0) begin + next_we_side = ~we_side; + end + end end // tready process always @* begin - next_tready = tready; - if (state == S_IDLE) begin - next_tready = 1'b1; - end else begin - if (read_window == 1'b1) begin - next_tready = 1'b1; - end else if (count_value == roll_over_offset && take_data == 1'b1 && take_data_d1 == 1'b1) begin - next_tready = 1'b0; - end else if (count_value == roll_over_m1 && take_data == 1'b1) begin - next_tready = 1'b0; - end + next_tready = tready; + if (state == S_IDLE) begin + next_tready = 1'b1; + end else begin + if (read_window == 1'b1) begin + next_tready = 1'b1; + end else if (count_value == roll_over_offset && take_data == 1'b1 && take_data_d1 == 1'b1) begin + next_tready = 1'b0; + end else if (count_value == roll_over_m1 && take_data == 1'b1) begin + next_tready = 1'b0; end + end end // read process. Controls the read pointers of the RAMs. Pushes data out of the input buffers // buffers. always @* begin - next_state = state; - next_rd_en = rd_en; - next_rd_side = rd_side; - next_read_addr = read_addr; - next_write_done = write_done; - case (state) - S_IDLE: - begin - if (write_d == 1'b1) begin - next_rd_en = 1'b1; - next_read_addr = 0; - next_state = S_READ; - next_rd_side = we_side; - next_write_done = 1'b0; - end - end - S_READ: - begin - if (read_addr == fft_max_slice) begin - if (write_d == 1'b1 || write_done == 1'b1) begin - next_rd_en = 1'b1; - next_read_addr = 0; - next_state = S_READ; - next_rd_side = ~rd_side; - next_write_done = 1'b0; - end else begin - next_state = S_IDLE; - next_rd_en = 1'b0; - end - end else begin - next_read_addr = read_addr + 1; - next_rd_en = 1'b1; - if (write_d == 1'b1) begin - next_write_done = 1'b1; - end - end + next_state = state; + next_rd_en = rd_en; + next_rd_side = rd_side; + next_read_addr = read_addr; + next_write_done = write_done; + case (state) + S_IDLE: + begin + if (write_d == 1'b1) begin + next_rd_en = 1'b1; + next_read_addr = 0; + next_state = S_READ; + next_rd_side = we_side; + next_write_done = 1'b0; + end + end + S_READ: + begin + if (read_addr == fft_max_slice) begin + if (write_d == 1'b1 || write_done == 1'b1) begin + next_rd_en = 1'b1; + next_read_addr = 0; + next_state = S_READ; + next_rd_side = ~rd_side; + next_write_done = 1'b0; + end else begin + next_state = S_IDLE; + next_rd_en = 1'b0; end - default : - begin + end else begin + next_read_addr = read_addr + 1; + next_rd_en = 1'b1; + if (write_d == 1'b1) begin + next_write_done = 1'b1; end - endcase + end + end + default : + begin + end + endcase end // output pipelining always @* begin - next_data = data; - next_phase = phase_s; - next_tvalid = rd_en_d[3]; // & rd_valid; - if (rd_en_d[3] == 1'b1) begin - // reading from top setp of buffers - next_phase = read_addr_d4; - if (rd_side_d[3] == 1'b0) begin - next_data = buffer_0; - end else begin - next_data = buffer_1; - end + next_data = data; + next_phase = phase_s; + next_tvalid = rd_en_d[3]; // & rd_valid; + if (rd_en_d[3] == 1'b1) begin + // reading from top setp of buffers + next_phase = read_addr_d4; + if (rd_side_d[3] == 1'b0) begin + next_data = buffer_0; + end else begin + next_data = buffer_1; end + end end // Block used for keeping track of input sample count. Performs roll-over at specifed point. @@ -287,5 +290,4 @@ input_buff_RAM buff_1 ( .doutb(buffer_1) // output wire [35 : 0] doutb ); - endmodule diff --git a/rfnoc/fpga-src/noc_block_channelizer.v b/rfnoc/fpga-src/noc_block_channelizer.v index a76fa61..82cbf67 100644 --- a/rfnoc/fpga-src/noc_block_channelizer.v +++ b/rfnoc/fpga-src/noc_block_channelizer.v @@ -1,7 +1,12 @@ - // -// Copyright 2015 Ettus Research +// Copyright 2016-2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 // +// Module: noc_block_channelizer +// Description: +// Top block for Channelization using RFNoC + module noc_block_channelizer #( parameter NOC_ID = 64'hF2A3373CFBFB4BFA, parameter STR_SINK_FIFOSIZE = 11) @@ -201,48 +206,48 @@ module noc_block_channelizer #( .o_tvalid(), .o_tready(1'b1)); - // FIR filter coefficient reload bus - // (see Xilinx FIR Filter Compiler documentation) - axi_setting_reg #( - .ADDR(SR_RELOAD), - .USE_ADDR_LAST(1), - .ADDR_LAST(SR_RELOAD_LAST), - .WIDTH(32), - .USE_FIFO(1), - .FIFO_SIZE(7)) - set_coeff ( - .clk(ce_clk), - .reset(ce_rst), - .set_stb(set_stb), - .set_addr(set_addr), - .set_data(set_data), - .o_tdata(m_axis_reload_tdata), - .o_tlast(m_axis_reload_tlast), - .o_tvalid(m_axis_reload_tvalid), - .o_tready(m_axis_reload_tready)); + // FIR filter coefficient reload bus + // (see Xilinx FIR Filter Compiler documentation) + axi_setting_reg #( + .ADDR(SR_RELOAD), + .USE_ADDR_LAST(1), + .ADDR_LAST(SR_RELOAD_LAST), + .WIDTH(32), + .USE_FIFO(1), + .FIFO_SIZE(7)) + set_coeff ( + .clk(ce_clk), + .reset(ce_rst), + .set_stb(set_stb), + .set_addr(set_addr), + .set_data(set_data), + .o_tdata(m_axis_reload_tdata), + .o_tlast(m_axis_reload_tlast), + .o_tvalid(m_axis_reload_tvalid), + .o_tready(m_axis_reload_tready)); channelizer_top channelizer_top ( - .sync_reset(ce_rst), - .ce_clk(ce_clk), - - .fft_size(fft_size), - - .s_axis_tdata(m_axis_data_tdata), - .s_axis_tvalid(m_axis_data_tvalid), - .s_axis_tready(m_axis_data_tready), - - .s_axis_reload_tdata(m_axis_reload_tdata), - .s_axis_reload_tlast(m_axis_reload_tlast), - .s_axis_reload_tvalid(m_axis_reload_tvalid), - .s_axis_reload_tready(m_axis_reload_tready), - - .eob_tag(eob_tag), - .m_axis_tdata(s_axis_data_tdata), - .m_axis_tuser(), - .m_axis_tvalid(s_axis_data_tvalid), - .m_axis_tlast(s_axis_data_tlast), - .m_axis_tready(s_axis_data_tready) + .sync_reset(ce_rst), + .ce_clk(ce_clk), + + .fft_size(fft_size), + + .s_axis_tdata(m_axis_data_tdata), + .s_axis_tvalid(m_axis_data_tvalid), + .s_axis_tready(m_axis_data_tready), + + .s_axis_reload_tdata(m_axis_reload_tdata), + .s_axis_reload_tlast(m_axis_reload_tlast), + .s_axis_reload_tvalid(m_axis_reload_tvalid), + .s_axis_reload_tready(m_axis_reload_tready), + + .eob_tag(eob_tag), + .m_axis_tdata(s_axis_data_tdata), + .m_axis_tuser(), + .m_axis_tvalid(s_axis_data_tvalid), + .m_axis_tlast(s_axis_data_tlast), + .m_axis_tready(s_axis_data_tready) ); endmodule diff --git a/rfnoc/fpga-src/pfb_2x.v b/rfnoc/fpga-src/pfb_2x.v index 10f5808..17dd610 100644 --- a/rfnoc/fpga-src/pfb_2x.v +++ b/rfnoc/fpga-src/pfb_2x.v @@ -1,34 +1,40 @@ -/*****************************************************************************/ +// +// Copyright 2016-2018 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0 +// +// Module: pfb_2x +// Description: // Implements the M/2 PFB architecture referenced in the // "A Versatile Multichannel Filter Bank with Multiple Channel Bandwidths" paper. // This architecture has been mapped to the Xilinx architecture. -// This represents a fully pipelined design that maximizes the FMax potential of the design. It is important -// to understand that filter arms are loaded sequentially. This is referenced in the diagram by the -// incremental changes in the phase subscript through each subsequent delay register. +// This represents a fully pipelined design that maximizes the FMax potential +// of the design. It is important to understand that filter arms are loaded +// sequentially. This is referenced in the diagram by the incremental changes +// in the phase subscript through each subsequent delay register. // The nth index is only updated once per revolution of the filter bank. // -// It is best to refer to the attached document to understand the layout of the logic. This module -// currently implements 24 taps per phase. -/*****************************************************************************/ +// It is best to refer to the attached document to understand the layout of the +// logic. This module currently implements 24 taps per phase. module pfb_2x ( - input sync_reset, - input clk, - - input [8:0] phase, - input [9:0] fft_size, - input [35:0] input_sig, - input valid_i, - - input [31:0] s_axis_reload_tdata, - input s_axis_reload_tlast, - input s_axis_reload_tvalid, - output s_axis_reload_tready, - - output [35:0] output_sig, - output [8:0] phase_out, - output valid_out //output valid signal. + input sync_reset, + input clk, + + input [8:0] phase, + input [9:0] fft_size, + input [35:0] input_sig, + input valid_i, + + input [31:0] s_axis_reload_tdata, + input s_axis_reload_tlast, + input s_axis_reload_tvalid, + output s_axis_reload_tready, + + output [35:0] output_sig, + output [8:0] phase_out, + output valid_out //output valid signal. ); wire [24:0] taps[0:23]; @@ -81,97 +87,96 @@ assign s_axis_reload_tready = reload_tready; integer n; always @(posedge clk) begin - - fft_max <= fft_size - 1; - fft_max_slice <= fft_max[8:0]; - fft_half <= fft_size >> 1; - - phase_d[0] <= rd_addr[8:0]; - phase_d[1] <= phase_d[0] & fft_max_slice; - phase_d[2] <= phase_d[1]; - s_axis_reload_tvalid_d1 <= s_axis_reload_tvalid; - - input_sig_d1 <= input_sig; - input_sig_d2 <= input_sig_d1; - input_sig_d3 <= input_sig_d2; - - wr_addr_d[0] <= wr_addr; - wr_addr_d[3] <= {~rd_addr[10], rd_addr[9], rd_addr[8:0]}; - wr_addr_d[6] <= {~rd_addr_d[0][10], rd_addr_d[0][9], rd_addr_d[0][8:0]}; - wr_addr_d[9] <= {~rd_addr_d[1][10], rd_addr_d[1][9], rd_addr_d[1][8:0]}; - wr_addr_d[12] <= {~rd_addr_d[2][10], rd_addr_d[2][9], rd_addr_d[2][8:0]}; - wr_addr_d[15] <= {~rd_addr_d[3][10], rd_addr_d[3][9], rd_addr_d[3][8:0]}; - wr_addr_d[18] <= {~rd_addr_d[4][10], rd_addr_d[4][9], rd_addr_d[4][8:0]}; - wr_addr_d[21] <= {~rd_addr_d[5][10], rd_addr_d[5][9], rd_addr_d[5][8:0]}; - wr_addr_d[24] <= {~rd_addr_d[6][10], rd_addr_d[6][9], rd_addr_d[6][8:0]}; - wr_addr_d[27] <= {~rd_addr_d[7][10], rd_addr_d[7][9], rd_addr_d[7][8:0]}; - wr_addr_d[30] <= {~rd_addr_d[8][10], rd_addr_d[8][9], rd_addr_d[8][8:0]}; - wr_addr_d[33] <= {~rd_addr_d[9][10], rd_addr_d[9][9], rd_addr_d[9][8:0]}; - wr_addr_d[36] <= {~rd_addr_d[10][10], rd_addr_d[10][9], rd_addr_d[10][8:0]}; - wr_addr_d[39] <= {~rd_addr_d[11][10], rd_addr_d[11][9], rd_addr_d[11][8:0]}; - wr_addr_d[42] <= {~rd_addr_d[12][10], rd_addr_d[12][9], rd_addr_d[12][8:0]}; - wr_addr_d[45] <= {~rd_addr_d[13][10], rd_addr_d[13][9], rd_addr_d[13][8:0]}; - wr_addr_d[48] <= {~rd_addr_d[14][10], rd_addr_d[14][9], rd_addr_d[14][8:0]}; - wr_addr_d[51] <= {~rd_addr_d[15][10], rd_addr_d[15][9], rd_addr_d[15][8:0]}; - wr_addr_d[54] <= {~rd_addr_d[16][10], rd_addr_d[16][9], rd_addr_d[16][8:0]}; - wr_addr_d[57] <= {~rd_addr_d[17][10], rd_addr_d[17][9], rd_addr_d[17][8:0]}; - wr_addr_d[60] <= {~rd_addr_d[18][10], rd_addr_d[18][9], rd_addr_d[18][8:0]}; - wr_addr_d[63] <= {~rd_addr_d[19][10], rd_addr_d[19][9], rd_addr_d[19][8:0]}; - wr_addr_d[66] <= {~rd_addr_d[20][10], rd_addr_d[20][9], rd_addr_d[20][8:0]}; - wr_addr_d[69] <= {~rd_addr_d[21][10], rd_addr_d[21][9], rd_addr_d[21][8:0]}; - - wr_addr_d[1] <= wr_addr_d[0]; - wr_addr_d[2] <= wr_addr_d[1]; - wr_addr_d[4] <= wr_addr_d[3]; - wr_addr_d[5] <= wr_addr_d[4]; - wr_addr_d[7] <= wr_addr_d[6]; - wr_addr_d[8] <= wr_addr_d[7]; - wr_addr_d[10] <= wr_addr_d[9]; - wr_addr_d[11] <= wr_addr_d[10]; - wr_addr_d[13] <= wr_addr_d[12]; - wr_addr_d[14] <= wr_addr_d[13]; - wr_addr_d[16] <= wr_addr_d[15]; - wr_addr_d[17] <= wr_addr_d[16]; - wr_addr_d[19] <= wr_addr_d[18]; - wr_addr_d[20] <= wr_addr_d[19]; - wr_addr_d[22] <= wr_addr_d[21]; - wr_addr_d[23] <= wr_addr_d[22]; - wr_addr_d[25] <= wr_addr_d[24]; - wr_addr_d[26] <= wr_addr_d[25]; - wr_addr_d[28] <= wr_addr_d[27]; - wr_addr_d[29] <= wr_addr_d[28]; - wr_addr_d[31] <= wr_addr_d[30]; - wr_addr_d[32] <= wr_addr_d[31]; - wr_addr_d[34] <= wr_addr_d[33]; - wr_addr_d[35] <= wr_addr_d[34]; - wr_addr_d[37] <= wr_addr_d[36]; - wr_addr_d[38] <= wr_addr_d[37]; - wr_addr_d[40] <= wr_addr_d[39]; - wr_addr_d[41] <= wr_addr_d[40]; - wr_addr_d[43] <= wr_addr_d[42]; - wr_addr_d[44] <= wr_addr_d[43]; - wr_addr_d[46] <= wr_addr_d[45]; - wr_addr_d[47] <= wr_addr_d[46]; - wr_addr_d[49] <= wr_addr_d[48]; - wr_addr_d[50] <= wr_addr_d[49]; - wr_addr_d[52] <= wr_addr_d[51]; - wr_addr_d[53] <= wr_addr_d[52]; - wr_addr_d[55] <= wr_addr_d[54]; - wr_addr_d[56] <= wr_addr_d[55]; - wr_addr_d[58] <= wr_addr_d[57]; - wr_addr_d[59] <= wr_addr_d[58]; - wr_addr_d[61] <= wr_addr_d[60]; - wr_addr_d[62] <= wr_addr_d[61]; - wr_addr_d[64] <= wr_addr_d[63]; - wr_addr_d[65] <= wr_addr_d[64]; - wr_addr_d[67] <= wr_addr_d[66]; - wr_addr_d[68] <= wr_addr_d[67]; - wr_addr_d[70] <= wr_addr_d[69]; - wr_addr_d[71] <= wr_addr_d[70]; - sig_d1 <= sig; - sig_d2 <= sig_d1; - sig_d3 <= sig_d2; - reload_tready <= 1'b1; + fft_max <= fft_size - 1; + fft_max_slice <= fft_max[8:0]; + fft_half <= fft_size >> 1; + + phase_d[0] <= rd_addr[8:0]; + phase_d[1] <= phase_d[0] & fft_max_slice; + phase_d[2] <= phase_d[1]; + s_axis_reload_tvalid_d1 <= s_axis_reload_tvalid; + + input_sig_d1 <= input_sig; + input_sig_d2 <= input_sig_d1; + input_sig_d3 <= input_sig_d2; + + wr_addr_d[0] <= wr_addr; + wr_addr_d[3] <= {~rd_addr[10], rd_addr[9], rd_addr[8:0]}; + wr_addr_d[6] <= {~rd_addr_d[0][10], rd_addr_d[0][9], rd_addr_d[0][8:0]}; + wr_addr_d[9] <= {~rd_addr_d[1][10], rd_addr_d[1][9], rd_addr_d[1][8:0]}; + wr_addr_d[12] <= {~rd_addr_d[2][10], rd_addr_d[2][9], rd_addr_d[2][8:0]}; + wr_addr_d[15] <= {~rd_addr_d[3][10], rd_addr_d[3][9], rd_addr_d[3][8:0]}; + wr_addr_d[18] <= {~rd_addr_d[4][10], rd_addr_d[4][9], rd_addr_d[4][8:0]}; + wr_addr_d[21] <= {~rd_addr_d[5][10], rd_addr_d[5][9], rd_addr_d[5][8:0]}; + wr_addr_d[24] <= {~rd_addr_d[6][10], rd_addr_d[6][9], rd_addr_d[6][8:0]}; + wr_addr_d[27] <= {~rd_addr_d[7][10], rd_addr_d[7][9], rd_addr_d[7][8:0]}; + wr_addr_d[30] <= {~rd_addr_d[8][10], rd_addr_d[8][9], rd_addr_d[8][8:0]}; + wr_addr_d[33] <= {~rd_addr_d[9][10], rd_addr_d[9][9], rd_addr_d[9][8:0]}; + wr_addr_d[36] <= {~rd_addr_d[10][10], rd_addr_d[10][9], rd_addr_d[10][8:0]}; + wr_addr_d[39] <= {~rd_addr_d[11][10], rd_addr_d[11][9], rd_addr_d[11][8:0]}; + wr_addr_d[42] <= {~rd_addr_d[12][10], rd_addr_d[12][9], rd_addr_d[12][8:0]}; + wr_addr_d[45] <= {~rd_addr_d[13][10], rd_addr_d[13][9], rd_addr_d[13][8:0]}; + wr_addr_d[48] <= {~rd_addr_d[14][10], rd_addr_d[14][9], rd_addr_d[14][8:0]}; + wr_addr_d[51] <= {~rd_addr_d[15][10], rd_addr_d[15][9], rd_addr_d[15][8:0]}; + wr_addr_d[54] <= {~rd_addr_d[16][10], rd_addr_d[16][9], rd_addr_d[16][8:0]}; + wr_addr_d[57] <= {~rd_addr_d[17][10], rd_addr_d[17][9], rd_addr_d[17][8:0]}; + wr_addr_d[60] <= {~rd_addr_d[18][10], rd_addr_d[18][9], rd_addr_d[18][8:0]}; + wr_addr_d[63] <= {~rd_addr_d[19][10], rd_addr_d[19][9], rd_addr_d[19][8:0]}; + wr_addr_d[66] <= {~rd_addr_d[20][10], rd_addr_d[20][9], rd_addr_d[20][8:0]}; + wr_addr_d[69] <= {~rd_addr_d[21][10], rd_addr_d[21][9], rd_addr_d[21][8:0]}; + + wr_addr_d[1] <= wr_addr_d[0]; + wr_addr_d[2] <= wr_addr_d[1]; + wr_addr_d[4] <= wr_addr_d[3]; + wr_addr_d[5] <= wr_addr_d[4]; + wr_addr_d[7] <= wr_addr_d[6]; + wr_addr_d[8] <= wr_addr_d[7]; + wr_addr_d[10] <= wr_addr_d[9]; + wr_addr_d[11] <= wr_addr_d[10]; + wr_addr_d[13] <= wr_addr_d[12]; + wr_addr_d[14] <= wr_addr_d[13]; + wr_addr_d[16] <= wr_addr_d[15]; + wr_addr_d[17] <= wr_addr_d[16]; + wr_addr_d[19] <= wr_addr_d[18]; + wr_addr_d[20] <= wr_addr_d[19]; + wr_addr_d[22] <= wr_addr_d[21]; + wr_addr_d[23] <= wr_addr_d[22]; + wr_addr_d[25] <= wr_addr_d[24]; + wr_addr_d[26] <= wr_addr_d[25]; + wr_addr_d[28] <= wr_addr_d[27]; + wr_addr_d[29] <= wr_addr_d[28]; + wr_addr_d[31] <= wr_addr_d[30]; + wr_addr_d[32] <= wr_addr_d[31]; + wr_addr_d[34] <= wr_addr_d[33]; + wr_addr_d[35] <= wr_addr_d[34]; + wr_addr_d[37] <= wr_addr_d[36]; + wr_addr_d[38] <= wr_addr_d[37]; + wr_addr_d[40] <= wr_addr_d[39]; + wr_addr_d[41] <= wr_addr_d[40]; + wr_addr_d[43] <= wr_addr_d[42]; + wr_addr_d[44] <= wr_addr_d[43]; + wr_addr_d[46] <= wr_addr_d[45]; + wr_addr_d[47] <= wr_addr_d[46]; + wr_addr_d[49] <= wr_addr_d[48]; + wr_addr_d[50] <= wr_addr_d[49]; + wr_addr_d[52] <= wr_addr_d[51]; + wr_addr_d[53] <= wr_addr_d[52]; + wr_addr_d[55] <= wr_addr_d[54]; + wr_addr_d[56] <= wr_addr_d[55]; + wr_addr_d[58] <= wr_addr_d[57]; + wr_addr_d[59] <= wr_addr_d[58]; + wr_addr_d[61] <= wr_addr_d[60]; + wr_addr_d[62] <= wr_addr_d[61]; + wr_addr_d[64] <= wr_addr_d[63]; + wr_addr_d[65] <= wr_addr_d[64]; + wr_addr_d[67] <= wr_addr_d[66]; + wr_addr_d[68] <= wr_addr_d[67]; + wr_addr_d[70] <= wr_addr_d[69]; + wr_addr_d[71] <= wr_addr_d[70]; + sig_d1 <= sig; + sig_d2 <= sig_d1; + sig_d3 <= sig_d2; + reload_tready <= 1'b1; end @@ -180,170 +185,170 @@ integer m; always @(posedge clk, posedge sync_reset) begin if (sync_reset == 1'b1) begin - offset_cnt <= 1; // this ensures that the first read / write is to offset 0. - offset_cnt_prev <= 0; - sig <= 0; - valid_d <= 0; - for (m=0; m<23; m=m+1) begin - rd_addr_d[m] <= 0; - end - new_coeffs <= 1'b1; - taps_addr <= 0; - rom_addr <= 0; - rom_data <= 0; - taps_we <= 0; - taps_dina <= 0; - rd_addr <= 0; - wr_addr <= 0; + offset_cnt <= 1; // this ensures that the first read / write is to offset 0. + offset_cnt_prev <= 0; + sig <= 0; + valid_d <= 0; + for (m=0; m<23; m=m+1) begin + rd_addr_d[m] <= 0; + end + new_coeffs <= 1'b1; + taps_addr <= 0; + rom_addr <= 0; + rom_data <= 0; + taps_we <= 0; + taps_dina <= 0; + rd_addr <= 0; + wr_addr <= 0; end else begin - offset_cnt <= next_offset_cnt; - offset_cnt_prev <= next_offset_cnt_prev; - sig <= next_sig; - valid_d <= {valid_d[6:0], valid_i}; - phase_d[0] <= phase; - for (m=0; m<23; m=m+1) begin - rd_addr_d[m] <= next_rd_addr_d[m]; - end - new_coeffs <= next_new_coeffs; - taps_addr <= next_taps_addr; - rom_addr <= next_rom_addr; - rom_data <= next_rom_data; - taps_we <= next_taps_we; - taps_dina <= next_taps_dina; - rd_addr <= next_rd_addr; - wr_addr <= next_wr_addr; + offset_cnt <= next_offset_cnt; + offset_cnt_prev <= next_offset_cnt_prev; + sig <= next_sig; + valid_d <= {valid_d[6:0], valid_i}; + phase_d[0] <= phase; + for (m=0; m<23; m=m+1) begin + rd_addr_d[m] <= next_rd_addr_d[m]; + end + new_coeffs <= next_new_coeffs; + taps_addr <= next_taps_addr; + rom_addr <= next_rom_addr; + rom_data <= next_rom_data; + taps_we <= next_taps_we; + taps_dina <= next_taps_dina; + rd_addr <= next_rd_addr; + wr_addr <= next_wr_addr; end end always @(posedge clk) begin - if (valid_d[6] == 1'b1) begin - phase_d[3] <= phase_d[2]; - phase_d[4] <= phase_d[3]; - phase_d[5] <= phase_d[4]; - phase_d[6] <= phase_d[5]; - phase_d[7] <= phase_d[6]; - phase_d[8] <= phase_d[7]; - phase_d[9] <= phase_d[8]; - phase_d[10] <= phase_d[9]; - phase_d[11] <= phase_d[10]; - phase_d[12] <= phase_d[11]; - phase_d[13] <= phase_d[12]; - phase_d[14] <= phase_d[13]; - phase_d[15] <= phase_d[14]; - phase_d[16] <= phase_d[15]; - phase_d[17] <= phase_d[16]; - phase_d[18] <= phase_d[17]; - phase_d[19] <= phase_d[18]; - phase_d[20] <= phase_d[19]; - phase_d[21] <= phase_d[20]; - phase_d[22] <= phase_d[21]; - phase_d[23] <= phase_d[22]; - phase_d[24] <= phase_d[23]; - phase_d[25] <= phase_d[24]; - phase_d[26] <= phase_d[25]; - phase_d[27] <= phase_d[26]; - phase_d[28] <= phase_d[27]; - phase_d[29] <= phase_d[28]; - end + if (valid_d[6] == 1'b1) begin + phase_d[3] <= phase_d[2]; + phase_d[4] <= phase_d[3]; + phase_d[5] <= phase_d[4]; + phase_d[6] <= phase_d[5]; + phase_d[7] <= phase_d[6]; + phase_d[8] <= phase_d[7]; + phase_d[9] <= phase_d[8]; + phase_d[10] <= phase_d[9]; + phase_d[11] <= phase_d[10]; + phase_d[12] <= phase_d[11]; + phase_d[13] <= phase_d[12]; + phase_d[14] <= phase_d[13]; + phase_d[15] <= phase_d[14]; + phase_d[16] <= phase_d[15]; + phase_d[17] <= phase_d[16]; + phase_d[18] <= phase_d[17]; + phase_d[19] <= phase_d[18]; + phase_d[20] <= phase_d[19]; + phase_d[21] <= phase_d[20]; + phase_d[22] <= phase_d[21]; + phase_d[23] <= phase_d[22]; + phase_d[24] <= phase_d[23]; + phase_d[25] <= phase_d[24]; + phase_d[26] <= phase_d[25]; + phase_d[27] <= phase_d[26]; + phase_d[28] <= phase_d[27]; + phase_d[29] <= phase_d[28]; + end end // reload process always @* begin - next_taps_addr = taps_addr; - next_taps_dina = taps_dina; - next_new_coeffs = new_coeffs; - - next_rom_addr = taps_addr[8:0]; - next_rom_data = taps_dina; - if (s_axis_reload_tvalid == 1'b1) begin - next_taps_dina = s_axis_reload_tdata[24:0]; - if (new_coeffs == 1'b1) begin - next_taps_addr = 0; - next_new_coeffs = 1'b0; - end else begin - next_taps_addr = taps_addr + 1; - if (s_axis_reload_tlast == 1'b1) begin - next_new_coeffs = 1'b1; - end - end - end - // implements the write address pointer for tap updates. - if (s_axis_reload_tvalid_d1 == 1'b1) begin - case (taps_addr[13:9]) - 5'd0: next_taps_we = 24'd1; - 5'd1: next_taps_we = 24'd2; - 5'd2: next_taps_we = 24'd4; - 5'd3: next_taps_we = 24'd8; - 5'd4: next_taps_we = 24'd16; - 5'd5: next_taps_we = 24'd32; - 5'd6: next_taps_we = 24'd64; - 5'd7: next_taps_we = 24'd128; - 5'd8: next_taps_we = 24'd256; - 5'd9: next_taps_we = 24'd512; - 5'd10: next_taps_we = 24'd1024; - 5'd11: next_taps_we = 24'd2048; - 5'd12: next_taps_we = 24'd4096; - 5'd13: next_taps_we = 24'd8192; - 5'd14: next_taps_we = 24'd16384; - 5'd15: next_taps_we = 24'd32768; - 5'd16: next_taps_we = 24'd65536; - 5'd17: next_taps_we = 24'd131072; - 5'd18: next_taps_we = 24'd262144; - 5'd19: next_taps_we = 24'd524288; - 5'd20: next_taps_we = 24'd1048576; - 5'd21: next_taps_we = 24'd2097152; - 5'd22: next_taps_we = 24'd4194304; - 5'd23: next_taps_we = 24'd8388608; - default: next_taps_we = 24'd0; - endcase + next_taps_addr = taps_addr; + next_taps_dina = taps_dina; + next_new_coeffs = new_coeffs; + + next_rom_addr = taps_addr[8:0]; + next_rom_data = taps_dina; + if (s_axis_reload_tvalid == 1'b1) begin + next_taps_dina = s_axis_reload_tdata[24:0]; + if (new_coeffs == 1'b1) begin + next_taps_addr = 0; + next_new_coeffs = 1'b0; end else begin - next_taps_we = 24'd0; + next_taps_addr = taps_addr + 1; + if (s_axis_reload_tlast == 1'b1) begin + next_new_coeffs = 1'b1; + end end + end + // implements the write address pointer for tap updates. + if (s_axis_reload_tvalid_d1 == 1'b1) begin + case (taps_addr[13:9]) + 5'd0: next_taps_we = 24'd1; + 5'd1: next_taps_we = 24'd2; + 5'd2: next_taps_we = 24'd4; + 5'd3: next_taps_we = 24'd8; + 5'd4: next_taps_we = 24'd16; + 5'd5: next_taps_we = 24'd32; + 5'd6: next_taps_we = 24'd64; + 5'd7: next_taps_we = 24'd128; + 5'd8: next_taps_we = 24'd256; + 5'd9: next_taps_we = 24'd512; + 5'd10: next_taps_we = 24'd1024; + 5'd11: next_taps_we = 24'd2048; + 5'd12: next_taps_we = 24'd4096; + 5'd13: next_taps_we = 24'd8192; + 5'd14: next_taps_we = 24'd16384; + 5'd15: next_taps_we = 24'd32768; + 5'd16: next_taps_we = 24'd65536; + 5'd17: next_taps_we = 24'd131072; + 5'd18: next_taps_we = 24'd262144; + 5'd19: next_taps_we = 24'd524288; + 5'd20: next_taps_we = 24'd1048576; + 5'd21: next_taps_we = 24'd2097152; + 5'd22: next_taps_we = 24'd4194304; + 5'd23: next_taps_we = 24'd8388608; + default: next_taps_we = 24'd0; + endcase + end else begin + next_taps_we = 24'd0; + end end // read and write address update logic. always @* begin - next_offset_cnt = offset_cnt; - next_offset_cnt_prev = offset_cnt_prev; - next_rd_addr = rd_addr; - next_wr_addr = wr_addr; - // increment offset count once per cycle through the PFB arms. - if (valid_d[2] == 1'b1) begin - if (phase_d[2] == 9'd0) begin - next_offset_cnt_prev = offset_cnt; - next_offset_cnt = offset_cnt + 1; - next_wr_addr = {offset_cnt + 1, phase_d[2]}; - next_rd_addr = {offset_cnt, phase_d[2]}; - end else begin - next_rd_addr = {offset_cnt_prev, phase_d[2]}; - next_wr_addr = {offset_cnt, phase_d[2]}; - end - end - - if (valid_d[2] == 1'b1) begin - if ((phase_d[2] & fft_half) != 8'd0) begin - next_sig = delay_sig; - end else begin - next_sig = input_sig_d3; - end + next_offset_cnt = offset_cnt; + next_offset_cnt_prev = offset_cnt_prev; + next_rd_addr = rd_addr; + next_wr_addr = wr_addr; + // increment offset count once per cycle through the PFB arms. + if (valid_d[2] == 1'b1) begin + if (phase_d[2] == 9'd0) begin + next_offset_cnt_prev = offset_cnt; + next_offset_cnt = offset_cnt + 1; + next_wr_addr = {offset_cnt + 1, phase_d[2]}; + next_rd_addr = {offset_cnt, phase_d[2]}; end else begin - next_sig = sig; + next_rd_addr = {offset_cnt_prev, phase_d[2]}; + next_wr_addr = {offset_cnt, phase_d[2]}; end + end - // shift through old values. - if (valid_d[2] == 1'b1) begin - next_rd_addr_d[0] = rd_addr; - for (n=1; n<23; n=n+1) begin - next_rd_addr_d[n] <= rd_addr_d[n-1]; - end + if (valid_d[2] == 1'b1) begin + if ((phase_d[2] & fft_half) != 8'd0) begin + next_sig = delay_sig; end else begin - for (n=0; n<23; n=n+1) begin - next_rd_addr_d[n] <= rd_addr_d[n]; - end + next_sig = input_sig_d3; + end + end else begin + next_sig = sig; + end + + // shift through old values. + if (valid_d[2] == 1'b1) begin + next_rd_addr_d[0] = rd_addr; + for (n=1; n<23; n=n+1) begin + next_rd_addr_d[n] <= rd_addr_d[n-1]; + end + end else begin + for (n=0; n<23; n=n+1) begin + next_rd_addr_d[n] <= rd_addr_d[n]; end + end end // 3 cycle latency. @@ -370,45 +375,45 @@ sample_ram sample_ram_0 ( genvar i; generate - for (i=1; i<24; i=i+1) begin : TAP_DELAY - sample_ram sample_ram_inst ( - .clka(clk), // input wire clka - .wea(valid_d[6]), // input wire [0 : 0] wea - .addra(wr_addr_d[i*3+2][10:0]), // input wire [13 : 0] addra - .dina(delay[i-1]), // input wire [35 : 0] dina - .clkb(clk), // input wire clkb - .addrb(rd_addr_d[i-1][10:0]), // input wire [13 : 0] addrb - .doutb(delay[i]) // output wire [35 : 0] doutb - ); - end + for (i=1; i<24; i=i+1) begin : TAP_DELAY + sample_ram sample_ram_inst ( + .clka(clk), // input wire clka + .wea(valid_d[6]), // input wire [0 : 0] wea + .addra(wr_addr_d[i*3+2][10:0]), // input wire [13 : 0] addra + .dina(delay[i-1]), // input wire [35 : 0] dina + .clkb(clk), // input wire clkb + .addrb(rd_addr_d[i-1][10:0]), // input wire [13 : 0] addrb + .doutb(delay[i]) // output wire [35 : 0] doutb + ); + end endgenerate // Coefficent memories // latency = 3. pfb_taps pfb_taps_0 ( - .clka(clk), - .wea(taps_we[0]), - .addra(rom_addr[8:0]), - .dina(rom_data), - .clkb(clk), // input wire clka - .addrb(rd_addr[8:0]), // input wire [11 : 0] addra - .doutb(taps[0]) // output wire [24 : 0] douta + .clka(clk), + .wea(taps_we[0]), + .addra(rom_addr[8:0]), + .dina(rom_data), + .clkb(clk), // input wire clka + .addrb(rd_addr[8:0]), // input wire [11 : 0] addra + .doutb(taps[0]) // output wire [24 : 0] douta ); genvar nn; generate - for (nn=1; nn<24; nn=nn+1) begin : COEFFS - pfb_taps pfb_taps_n - ( - .clka(clk), - .wea(taps_we[nn]), - .addra(rom_addr[8:0]), - .dina(rom_data), - .clkb(clk), // input wire clka - .addrb(rd_addr_d[nn-1][8:0]), // input wire [7 : 0] addra - .doutb(taps[nn]) // output wire [24 : 0] douta - ); - end + for (nn=1; nn<24; nn=nn+1) begin : COEFFS + pfb_taps pfb_taps_n + ( + .clka(clk), + .wea(taps_we[nn]), + .addra(rom_addr[8:0]), + .dina(rom_data), + .clkb(clk), // input wire clka + .addrb(rd_addr_d[nn-1][8:0]), // input wire [7 : 0] addra + .doutb(taps[nn]) // output wire [24 : 0] douta + ); + end endgenerate @@ -434,29 +439,29 @@ pfb_mac_0 pfb_mac_q_start ( genvar j; generate - for (j=1; j<23; j=j+1) begin : MAC - pfb_mac pfb_mac_i - ( - .CLK(clk), // input wire CLK - .CE(valid_d[6]), // input wire CE - .PCIN(pcouti[j-1]), // input wire [47 : 0] PCIN - .A(taps[j]), // input wire [24 : 0] A - .B(delay[j][35:18]), // input wire [17 : 0] B - .PCOUT(pcouti[j]), // output wire [47 : 0] PCOUT - .P() // output wire [47 : 0] P - ); - - pfb_mac pfb_mac_q - ( - .CLK(clk), // input wire CLK - .CE(valid_d[6]), // input wire CE - .PCIN(pcoutq[j-1]), // input wire [47 : 0] PCIN - .A(taps[j]), // input wire [24 : 0] A - .B(delay[j][17:0]), // input wire [17 : 0] B - .PCOUT(pcoutq[j]), // output wire [47 : 0] PCOUT - .P() // output wire [47 : 0] P - ); - end + for (j=1; j<23; j=j+1) begin : MAC + pfb_mac pfb_mac_i + ( + .CLK(clk), // input wire CLK + .CE(valid_d[6]), // input wire CE + .PCIN(pcouti[j-1]), // input wire [47 : 0] PCIN + .A(taps[j]), // input wire [24 : 0] A + .B(delay[j][35:18]), // input wire [17 : 0] B + .PCOUT(pcouti[j]), // output wire [47 : 0] PCOUT + .P() // output wire [47 : 0] P + ); + + pfb_mac pfb_mac_q + ( + .CLK(clk), // input wire CLK + .CE(valid_d[6]), // input wire CE + .PCIN(pcoutq[j-1]), // input wire [47 : 0] PCIN + .A(taps[j]), // input wire [24 : 0] A + .B(delay[j][17:0]), // input wire [17 : 0] B + .PCOUT(pcoutq[j]), // output wire [47 : 0] PCOUT + .P() // output wire [47 : 0] P + ); + end endgenerate pfb_mac pfb_mac_i_23 ( @@ -479,5 +484,4 @@ pfb_mac pfb_mac_q_23 ( .P(poutq) // output wire [42 : 0] P ); - endmodule From b20892d0b15b45dcdb81968e3ddbbb730cc63157 Mon Sep 17 00:00:00 2001 From: Nicolas Cuervo Date: Wed, 14 Mar 2018 23:59:23 +0100 Subject: [PATCH 4/5] lib: minor indentation fixes and removal of superfluous comments --- lib/chanmux_block_ctrl_impl.cpp | 28 ++--------------------- lib/chanmux_impl.cc | 40 ++++++++++++++------------------- lib/chanmux_impl.h | 3 --- lib/poly_channelizer_impl.cc | 2 +- lib/poly_channelizer_impl.h | 2 +- 5 files changed, 21 insertions(+), 54 deletions(-) diff --git a/lib/chanmux_block_ctrl_impl.cpp b/lib/chanmux_block_ctrl_impl.cpp index 2ddb950..f56b96d 100644 --- a/lib/chanmux_block_ctrl_impl.cpp +++ b/lib/chanmux_block_ctrl_impl.cpp @@ -1,6 +1,6 @@ /* -*- c++ -*- */ /* - * Copyright 2017 <+YOU OR YOUR COMPANY+>. + * Copyright 2017-2018 Ettus Research * * This is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -119,7 +119,7 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl sr_write(SR_RELOAD, boost::uint32_t(taps_fi[i])); printf("tap[%d] = %d\n", (int) i, (int) boost::uint32_t(taps_fi[i])); } - sr_write(SR_RELOAD_TLAST, boost::uint32_t(taps_fi.back())); + sr_write(SR_RELOAD_TLAST, boost::uint32_t(taps_fi.back())); printf("final tap = %d\n", (int) boost::uint32_t(taps_fi.back())); printf("set_taps() done\n"); } @@ -146,7 +146,6 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl } } - int nextpow2(const int value) { @@ -212,7 +211,6 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl } int N = A_vals.size(); - // idx = np.arange(N / 2) for (int i=0; i < N / 2; i++) { @@ -227,9 +225,6 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl { A_vals[i] = std::pow(A_vals[i], exponent); } - // cast A as complex. - // gr_complex *A_complex = new gr_complex; - // volk_32f_x2_interleave_32fc(A_complex, &A_vals[0], q_a, A_vals.size()); int fil_size = (int) A_vals.size(); gr::fft::fft_complex *d_fwdfft = new gr::fft::fft_complex(fil_size, false, 1); @@ -243,7 +238,6 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl { temp_grc = (gr_complex) A_vals[j]; A_comp.push_back(temp_grc); - // printf("A_comp[%d] = %f + j%f;\n", j, temp_grc.real(), temp_grc.imag()); } // copy A values into fft input buffer @@ -254,7 +248,6 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl gr_complex *b = d_fwdfft->get_outbuf(); gr_complex *b_copy; - // memcpy(b_copy, b, fft_size); // perform shift int shift_pt = fil_size >> 1; float sum_b = 0.; @@ -271,19 +264,12 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl { ret_val[i] = ret_val[i] / sum_b; } - // take real part of b. - // - - // b = np.fft.ifft(A) - // b = (np.fft.fftshift(b)).real - // b /= np.sum(b) delete d_fwdfft; } void gen_fixed_filter(const gr_vector_float& taps, const int fft_size, const int desired_msb, gr_vector_int& output_vector) { - // float max_coeff_val = (2. **(qvec_coef[0] - 1) - 1) * (2. ** -self.qvec_coef[1]) float max_coeff_val = (std::pow(2., (float) qvec_coef[0] - 1.) - 1.) * std::pow(2., (float)-qvec_coef[1]); int max_input = (int) std::pow(2., (float) qvec[0] - 1.) - 1; @@ -333,14 +319,10 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl s_gain = std::max_element(path_gain.begin(), path_gain.end()); // // compute noise and signal gain. int gain_msb = nextpow2(*s_gain); - // - // gain_msb = self.nextpow2(s_gain) int max_coef_val = (int) std::pow(2., (float) gain_msb - 1.); float in_use = (float) *s_gain / (float) max_coef_val; - // // print(np.max(s_gain), np.max(max_input)) int int_max_value = *s_gain * max_input; int num_bits = ret_num_bitsS(int_max_value); - // // print(num_bits) int msb = num_bits - 1; if (in_use <= .9) { @@ -356,7 +338,6 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl } } } - // if (desired_msb < msb) { int diff = msb - desired_msb; @@ -371,10 +352,6 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl // reshape poly_fi into single vector with padding. int pad = max_fft_size - fft_size; - // // print("msb = {}".format(msb)) - // // taps_fi = np.reshape(poly_fil, (1, -1), order='F') - // poly_fil = poly_fil.astype(np.int32) - // for (int j=0; j < taps_per_phase; j++) { for (int i=0; i < fft_size; i++) @@ -390,7 +367,6 @@ class chanmux_block_ctrl_impl : public chanmux_block_ctrl printf("output_vector[i] = %d\n", output_vector[i]); } } - }; UHD_RFNOC_BLOCK_REGISTER(chanmux_block_ctrl,"chanmux"); diff --git a/lib/chanmux_impl.cc b/lib/chanmux_impl.cc index 581343d..a8a2b0b 100644 --- a/lib/chanmux_impl.cc +++ b/lib/chanmux_impl.cc @@ -49,9 +49,9 @@ namespace gr { * The private constructor */ chanmux_impl::chanmux_impl( - const gr::ettus::device3::sptr &dev, - const int block_select, - const int device_select + const gr::ettus::device3::sptr &dev, + const int block_select, + const int device_select ) : gr::ettus::rfnoc_block("chanmux"), gr::ettus::rfnoc_block_impl( @@ -71,27 +71,21 @@ namespace gr { { } + void + chanmux_impl::set_block_size(const int fft_size) + { + gr::thread::scoped_lock guard(d_mutex); + get_block_ctrl_throw< ::uhd::rfnoc::chanmux_block_ctrl>()-> set_fft_size(fft_size); -void -chanmux_impl::set_block_size(const int fft_size) -{ - gr::thread::scoped_lock guard(d_mutex); - get_block_ctrl_throw< ::uhd::rfnoc::chanmux_block_ctrl>()-> set_fft_size(fft_size); - - // read back to ensure HW and SW are in sync. - d_fft_size = get_block_ctrl_throw< ::uhd::rfnoc::chanmux_block_ctrl >()->get_fft_size(); - // now always pulling blocks of 256 samples. - -} - - -void -chanmux_impl::get_block_size() -{ - d_fft_size = get_block_ctrl_throw< ::uhd::rfnoc::chanmux_block_ctrl >()-> get_fft_size(); -} - - + // read back to ensure HW and SW are in sync. + d_fft_size = get_block_ctrl_throw< ::uhd::rfnoc::chanmux_block_ctrl >()->get_fft_size(); + // now always pulling blocks of 256 samples. + } + void + chanmux_impl::get_block_size() + { + d_fft_size = get_block_ctrl_throw< ::uhd::rfnoc::chanmux_block_ctrl >()-> get_fft_size(); + } } /* namespace pfb_channelizer */ } /* namespace gr */ diff --git a/lib/chanmux_impl.h b/lib/chanmux_impl.h index c47dc92..86d171f 100644 --- a/lib/chanmux_impl.h +++ b/lib/chanmux_impl.h @@ -33,7 +33,6 @@ namespace gr { private: size_t d_fft_size; gr::thread::mutex d_mutex; // mutex to protect set/work access - // int nextpow2(unsigned int i); public: chanmux_impl(const gr::ettus::device3::sptr &dev, const int block_select, const int device_select); @@ -41,8 +40,6 @@ namespace gr { void set_block_size(const int fft_size); void get_block_size(); - // Where all the action really happens - // void forecast (int noutput_items, gr_vector_int &ninput_items_required); }; } // namespace pfb_channelizer diff --git a/lib/poly_channelizer_impl.cc b/lib/poly_channelizer_impl.cc index 5b3e219..dcab95c 100644 --- a/lib/poly_channelizer_impl.cc +++ b/lib/poly_channelizer_impl.cc @@ -1,6 +1,6 @@ /* -*- c++ -*- */ /* - * Copyright 2017 <+YOU OR YOUR COMPANY+>. + * Copyright 2017-2018 Ettus Research * * This is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/lib/poly_channelizer_impl.h b/lib/poly_channelizer_impl.h index b4e5518..6aef376 100644 --- a/lib/poly_channelizer_impl.h +++ b/lib/poly_channelizer_impl.h @@ -1,6 +1,6 @@ /* -*- c++ -*- */ /* - * Copyright 2017 <+YOU OR YOUR COMPANY+>. + * Copyright 2017-2018 Ettus Research * * This is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by From 5e21c25b4fc3ec5118612ac034b2b6259ea57913 Mon Sep 17 00:00:00 2001 From: Nicolas Cuervo Date: Thu, 15 Mar 2018 00:02:04 +0100 Subject: [PATCH 5/5] Removed precompiled headers and orig files --- include/pfb_channelizer/chanmux.h.gch | Bin 9475 -> 0 bytes .../chanmux_block_ctrl.hpp.gch | Bin 9475 -> 0 bytes .../pfb_channelizer/poly_channelizer.h.gch | Bin 9475 -> 0 bytes lib/poly_channelizer_impl.cc.orig | 157 ------------------ lib/poly_channelizer_impl.h.gch | Bin 9475 -> 0 bytes 5 files changed, 157 deletions(-) delete mode 100644 include/pfb_channelizer/chanmux.h.gch delete mode 100644 include/pfb_channelizer/chanmux_block_ctrl.hpp.gch delete mode 100644 include/pfb_channelizer/poly_channelizer.h.gch delete mode 100644 lib/poly_channelizer_impl.cc.orig delete mode 100644 lib/poly_channelizer_impl.h.gch diff --git a/include/pfb_channelizer/chanmux.h.gch b/include/pfb_channelizer/chanmux.h.gch deleted file mode 100644 index e4bf2984d99e2ab98701cf72f988de8b79277b4f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9475 zcmb7K$#Uz)6@AJ)InF!}u${zGY_ZUo2rMB2lu(99ngpNpyy@bjAU&2TN+Bsn&OXch zPxkqNd_$J`gDg^&d-?+C1}Q%~s-gxo(0zw<&mEwf`}xIsu`U1c-@m{4R&nyHfB)xS z@Bh{L=x@&so~f^YzVWX5?V$Sm887Vo$@iMy51u`S!ExYK*Yy3>#$V=zX4kzx559y; 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either version 3, or (at your option) - * any later version. - * - * This software is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this software; see the file COPYING. If not, write to - * the Free Software Foundation, Inc., 51 Franklin Street, - * Boston, MA 02110-1301, USA. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include -#include "poly_channelizer_impl.h" -#include -#include - - -namespace gr { - namespace pfb_channelizer { - - static const pmt::pmt_t EOB_KEY = pmt::string_to_symbol("rx_eob"); - - poly_channelizer::sptr - poly_channelizer::make(const int fft_size, const std::vector &map) - { - return gnuradio::get_initial_sptr(new poly_channelizer_impl(fft_size, map)); - } - - /* - * The private constructor - */ - poly_channelizer_impl::poly_channelizer_impl(const int fft_size, const std::vector &map) - : gr::block("poly_channelizer", - gr::io_signature::make(1, 1, sizeof(gr_complex)), - gr::io_signature::make(1, 512, sizeof(gr_complex))) - { - d_fft_size = fft_size; - gr::thread::scoped_lock guard(d_mutex); - // gr::block::set_max_noutput_items(256); - - if (map.size() > 0) { - unsigned int max = (unsigned int)*std::max_element(map.begin(), map.end()); - d_channel_map = map; - } - - set_tag_propagation_policy(TPP_DONT); - } - - /* - * Our virtual destructor. - */ - poly_channelizer_impl::~poly_channelizer_impl() - { - } - - void - poly_channelizer_impl::forecast (int noutput_items, gr_vector_int &ninput_items_required) - { - ninput_items_required[0] = d_fft_size; // * noutput_items; - } - - void - poly_channelizer_impl::set_block_size(const int fft_size) - { - gr::thread::scoped_lock guard(d_mutex); - d_fft_size = fft_size; - } - - int - poly_channelizer_impl::get_block_size() - { - return d_fft_size; - } - - std::vector - poly_channelizer_impl::get_channel_map() const - { - return d_channel_map; - } - - void - poly_channelizer_impl::set_channel_map(const std::vector& map) - { - gr::thread::scoped_lock guard(d_mutex); - - // std::cout << "map.size() = "<< (int) map.size() << std::endl; - // // * (int) d_fft_size); - if (map.size() > 0) { - unsigned int max = (unsigned int)*std::max_element(map.begin(), map.end()); - d_channel_map = map; - } - } - - int - poly_channelizer_impl::general_work(int noutput_items, - gr_vector_int& ninput_items, - gr_vector_const_void_star& input_items, - gr_vector_void_star& output_items) - { - gr::thread::scoped_lock guard(d_mutex); - - const gr_complex *in = (gr_complex *)input_items[0]; - gr_complex *out = (gr_complex *)output_items[0]; - std::vector tags; - std::vector::iterator ti; - int in_idx = 0; - int num_consumed = 0; - get_tags_in_range(tags, 0, nitems_read(0), nitems_read(0) + noutput_items, EOB_KEY); - int oo = 0; - size_t noutputs = output_items.size(); - for (ti = tags.begin(); ti != tags.end(); ti++) { - tag_t tag = *ti; - uint32_t burst_sz = (uint32_t)(tag.offset - nitems_read(0) - in_idx + 1); - - if (oo == noutput_items) { - std::cout << "breaking loop "<< std::endl; - break; - } - else - { - num_consumed += burst_sz; - if (burst_sz == d_fft_size) { - - for (unsigned int nn = 0; nn < noutputs; nn++) { - out = (gr_complex *)output_items[nn]; - out[oo] = in[in_idx + d_channel_map[nn]]; - } - oo++; - } - else { - std::cout << "burst_sz = " << (int) burst_sz << " Dropping Data" << std::endl; - } - in_idx += burst_sz; - } - } - consume_each(num_consumed); - for (unsigned int nn = 0; nn < noutputs; nn++) { - produce(nn, oo); - } - return num_consumed; - } - - } /* namespace pfb_channelizer */ -} /* namespace gr */ diff --git a/lib/poly_channelizer_impl.h.gch b/lib/poly_channelizer_impl.h.gch deleted file mode 100644 index e4bf2984d99e2ab98701cf72f988de8b79277b4f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 9475 zcmb7K$#Uz)6@AJ)InF!}u${zGY_ZUo2rMB2lu(99ngpNpyy@bjAU&2TN+Bsn&OXch zPxkqNd_$J`gDg^&d-?+C1}Q%~s-gxo(0zw<&mEwf`}xIsu`U1c-@m{4R&nyHfB)xS z@Bh{L=x@&so~f^YzVWX5?V$Sm887Vo$@iMy51u`S!ExYK*Yy3>#$V=zX4kzx559y; z>bZkj7(Sfk;Rp5}GcT*(n-dPcX090mnV0L|51!qWt8%@Vw~waf@6qSG^pSEh8Ocd8 z9u7{WwA`Q4wKvuE<~LynNV}8_Tin(2jmd zOFvS}(`-=4JdG!X2;_NuNn6;D*Yx#+W{0>Ko@YH7_dc9vV9Q> zQ65&C#m%a`vgWU5Yit6k$Q0Q}>98;R`7ka*o9+_B!!?y?{I!(&8>Idv2r~0 zhFXKRp`qr_=<0XW$_4CT>JJ-Ce?eL~W;@$1=5n^#lHgSB#Q@-%yGT9Xq``i;CrXwBz#SCh{J+j^v>dOb7z-txc)h1dMWLv>7gEc_(-9WBD3Qo`0}@$*zpUJQE5+VMD*@gR|ti+Ci3CBE>z&i`?*XNfMI z&u#)TlXNf~pI0ckx_fxJEDya-5GOJtR zR9P+`_CApPaY}GSl(10^{8BFtf8 z4}vk}xS@}IzCj-;Re*8q9npo|$bPLx(7uY3v$2jwp#P7}Qm*(;5fzb67SPkCuSP8+#EXTCo}=eV7X=Ldu8Lg6;>^Fwx^EdSKV{Q-Bh85!x@6?bC5~o(>8^ zZtwEa26YR7-6S+Z1;KfWjrp>Qj+3mQ%c17Q$qwB>?-miMeGZSMG>Pfh5=SsGbXT4y z?;5mg(dFN$B?Mj-oueUX2cFdN0eXBgkSHUy0_i7oBS+L>bjl@MP6)Ru3F05DqNCmwB5S`cOyE8cShv(yDyiKE+kI zUJ({-1jITGyoTafk~@h9D|V9arVD zyrB|gbtC6@tIc-(FyG#-RZSPzo=x{@7_$khgey8!j0KS^TrUiWC;hG+3cq~MwZr^K z6BTmZdiH0kbJlc*+P5ogD8w|5@PNYEpq~x0;sqo`@HVb9*u6$#ov&08R^iO3-e?OC z<&(*jW_(885$wf8-uO{l+@i(Z9Mgmh7qXB*aVKv=2$RUIAQvt&6_*o*8zEARvmW_o zFv*}J9%ReT@0Sl7d=LQ?zqu}?mGR1J`KO23a&f&V*)L>2P@q0qo>60Wej&O0P3pF1kXN!IT-sj60{ak`G4+3i(8#i4el;*`Nq7H8u$P9``T zLbEfCv+K4a@O?LE#VqK{{{ub4;8C%rzM1qexO_q zT|1%zAAEyznLsNa)FlBWBQpdkhfj;Xq&OvLfTXxO;tWyAvUzn!ofyTgRxckB3(*s> zI8$v+TP^n2*`dx+Cs`u<)T_jbiuHk20D+Zg+w?e~q@Co@f-N*oPctet#<~*0u`Fzr z7HdEPgj)StF3n~zyMFNLE*L0aw^8t9gFG9k)S?56$B7jNX;q2SyxksAy)wVM zDkU2J*_;|KPD8eb*m!5Vd>?j}J!4NY4&j z>W=q_+{}*T9Or01R%v%rP7?2sj^SWX%GC3oRuq})AP(7KiVU~gg(ae>D+HWXWeton z%wx>wks>sZjj{j{V198M%R7>p8^{}D9|ST-+JvgeDl=3ElWID}qlOa`(AU!%~=cjIG9zc*|y5rD(S%v z+!rcUIHpCY3t>(cFe~DLvlwv*S#>f!!DI(x6UB^n2YrxTRV)A;JFSTxdZt#wL;!xD z<`_oo0`xWErpdi7!dv8yopg5LYrmZ>&uEt_%~TTWHGnA=f_G#uop zd+mgF;ef9w^)u|DjPmriCYNX*)!LX9cDpdC`Oz3g*;Hgc!B#s3t_lC&lkgmKBzzN{ zd+8u`LoZ1%3*dOdkU;Osx!2rQmm#BZe0m;J-AE*j1eIPEgZP{ZNYI%sENUJyeV~0; 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