Counter.vhd.bak

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity count is
Generic (Number_Of_Words: natural := 32);
	port
	(
		clk		: in std_logic;
		updown		: in std_logic;
		reset	: in std_logic;
		enable 	: in std_logic;
		q		: out integer range 0 to Number_Of_Words;
		mem_input_clk : out std_logic
	);
end entity;

architecture rtl of count is
begin
	process (clk)
		variable   cnt	: integer range 0 to Number_Of_Words;
	begin
		if (rising_edge(clk)) then
			if reset = '1' then
				-- Reset the counter to 0
				cnt := 0;
			elsif enable = '1' then
				if updown = '1' then
					-- Increment the counter if counting is up
					cnt := cnt + 1;
				else
				-- Decrement the counter if counting is down
					cnt := cnt - 1;
				end if;
			end if;
		end if;
		
		-- Output the current count
		q <= cnt;
		-- Clock the memory
		mem_input_clk<='1';
	end process;

end rtl;