From b73e168ca5e123dcf3dea8a34b19a5130f421ae1 Mon Sep 17 00:00:00 2001 From: Viktoria Maximova Date: Wed, 28 Feb 2024 17:41:29 +0100 Subject: [PATCH 1/6] Headers support for SPV_INTEL_maximum_registers extension (#416) * Headers support for SPV_INTEL_maximum_registers extension * Use an operand kind for the named maximum number of registers * apply CI suggestions --- include/spirv/unified1/spirv.bf | 9 ++++ .../spirv/unified1/spirv.core.grammar.json | 45 +++++++++++++++++++ include/spirv/unified1/spirv.cs | 9 ++++ include/spirv/unified1/spirv.h | 9 ++++ include/spirv/unified1/spirv.hpp | 9 ++++ include/spirv/unified1/spirv.hpp11 | 9 ++++ include/spirv/unified1/spirv.json | 16 ++++++- include/spirv/unified1/spirv.lua | 8 ++++ include/spirv/unified1/spirv.py | 8 ++++ include/spirv/unified1/spv.d | 9 ++++ tools/buildHeaders/jsonToSpirv.cpp | 5 +++ tools/buildHeaders/jsonToSpirv.h | 1 + 12 files changed, 135 insertions(+), 2 deletions(-) diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf index ea185bfe5..c1fa60bba 100644 --- a/include/spirv/unified1/spirv.bf +++ b/include/spirv/unified1/spirv.bf @@ -212,6 +212,9 @@ namespace Spv StreamingInterfaceINTEL = 6154, RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, + MaximumRegistersINTEL = 6461, + MaximumRegistersIdINTEL = 6462, + NamedMaximumRegistersINTEL = 6463, } [AllowDuplicates, CRepr] public enum StorageClass @@ -1230,6 +1233,7 @@ namespace Spv GroupUniformArithmeticKHR = 6400, MaskedGatherScatterINTEL = 6427, CacheControlsINTEL = 6441, + RegisterLimitsINTEL = 6460, } [AllowDuplicates, CRepr] public enum RayFlagsShift @@ -1400,6 +1404,11 @@ namespace Spv StreamingINTEL = 3, } + [AllowDuplicates, CRepr] public enum NamedMaximumNumberOfRegisters + { + AutoINTEL = 0, + } + [AllowDuplicates, CRepr] public enum Op { OpNop = 0, diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json index 03f35957f..ba4493352 100644 --- a/include/spirv/unified1/spirv.core.grammar.json +++ b/include/spirv/unified1/spirv.core.grammar.json @@ -11660,6 +11660,33 @@ ], "capabilities" : [ "VectorComputeINTEL" ], "version" : "None" + }, + { + "enumerant" : "MaximumRegistersINTEL", + "value" : 6461, + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'Number of Registers'" } + ], + "capabilities" : [ "RegisterLimitsINTEL" ], + "version" : "None" + }, + { + "enumerant" : "MaximumRegistersIdINTEL", + "value" : 6462, + "parameters" : [ + { "kind" : "IdRef", "name" : "'Number of Registers'" } + ], + "capabilities" : [ "RegisterLimitsINTEL" ], + "version" : "None" + }, + { + "enumerant" : "NamedMaximumRegistersINTEL", + "value" : 6463, + "parameters" : [ + { "kind" : "NamedMaximumNumberOfRegisters", "name" : "'Named Maximum Number of Registers'" } + ], + "capabilities" : [ "RegisterLimitsINTEL" ], + "version" : "None" } ] }, @@ -16497,6 +16524,12 @@ "value" : 6441, "extensions" : [ "SPV_INTEL_cache_controls" ], "version" : "None" + }, + { + "enumerant" : "RegisterLimitsINTEL", + "value" : 6460, + "extensions" : [ "SPV_INTEL_maximum_registers" ], + "version" : "None" } ] }, @@ -16734,6 +16767,18 @@ } ] }, + { + "category" : "ValueEnum", + "kind" : "NamedMaximumNumberOfRegisters", + "enumerants" : [ + { + "enumerant" : "AutoINTEL", + "value" : 0, + "capabilities" : [ "RegisterLimitsINTEL" ], + "version" : "None" + } + ] + }, { "category" : "Id", "kind" : "IdResultType", diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs index 7922f1827..a91f4ff44 100644 --- a/include/spirv/unified1/spirv.cs +++ b/include/spirv/unified1/spirv.cs @@ -211,6 +211,9 @@ public enum ExecutionMode StreamingInterfaceINTEL = 6154, RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, + MaximumRegistersINTEL = 6461, + MaximumRegistersIdINTEL = 6462, + NamedMaximumRegistersINTEL = 6463, } public enum StorageClass @@ -1229,6 +1232,7 @@ public enum Capability GroupUniformArithmeticKHR = 6400, MaskedGatherScatterINTEL = 6427, CacheControlsINTEL = 6441, + RegisterLimitsINTEL = 6460, } public enum RayFlagsShift @@ -1399,6 +1403,11 @@ public enum StoreCacheControl StreamingINTEL = 3, } + public enum NamedMaximumNumberOfRegisters + { + AutoINTEL = 0, + } + public enum Op { OpNop = 0, diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h index 96928b11e..9276b301b 100644 --- a/include/spirv/unified1/spirv.h +++ b/include/spirv/unified1/spirv.h @@ -219,6 +219,9 @@ typedef enum SpvExecutionMode_ { SpvExecutionModeStreamingInterfaceINTEL = 6154, SpvExecutionModeRegisterMapInterfaceINTEL = 6160, SpvExecutionModeNamedBarrierCountINTEL = 6417, + SpvExecutionModeMaximumRegistersINTEL = 6461, + SpvExecutionModeMaximumRegistersIdINTEL = 6462, + SpvExecutionModeNamedMaximumRegistersINTEL = 6463, SpvExecutionModeMax = 0x7fffffff, } SpvExecutionMode; @@ -1229,6 +1232,7 @@ typedef enum SpvCapability_ { SpvCapabilityGroupUniformArithmeticKHR = 6400, SpvCapabilityMaskedGatherScatterINTEL = 6427, SpvCapabilityCacheControlsINTEL = 6441, + SpvCapabilityRegisterLimitsINTEL = 6460, SpvCapabilityMax = 0x7fffffff, } SpvCapability; @@ -1397,6 +1401,11 @@ typedef enum SpvStoreCacheControl_ { SpvStoreCacheControlMax = 0x7fffffff, } SpvStoreCacheControl; +typedef enum SpvNamedMaximumNumberOfRegisters_ { + SpvNamedMaximumNumberOfRegistersAutoINTEL = 0, + SpvNamedMaximumNumberOfRegistersMax = 0x7fffffff, +} SpvNamedMaximumNumberOfRegisters; + typedef enum SpvOp_ { SpvOpNop = 0, SpvOpUndef = 1, diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp index 012df1f05..327000af9 100644 --- a/include/spirv/unified1/spirv.hpp +++ b/include/spirv/unified1/spirv.hpp @@ -215,6 +215,9 @@ enum ExecutionMode { ExecutionModeStreamingInterfaceINTEL = 6154, ExecutionModeRegisterMapInterfaceINTEL = 6160, ExecutionModeNamedBarrierCountINTEL = 6417, + ExecutionModeMaximumRegistersINTEL = 6461, + ExecutionModeMaximumRegistersIdINTEL = 6462, + ExecutionModeNamedMaximumRegistersINTEL = 6463, ExecutionModeMax = 0x7fffffff, }; @@ -1225,6 +1228,7 @@ enum Capability { CapabilityGroupUniformArithmeticKHR = 6400, CapabilityMaskedGatherScatterINTEL = 6427, CapabilityCacheControlsINTEL = 6441, + CapabilityRegisterLimitsINTEL = 6460, CapabilityMax = 0x7fffffff, }; @@ -1393,6 +1397,11 @@ enum StoreCacheControl { StoreCacheControlMax = 0x7fffffff, }; +enum NamedMaximumNumberOfRegisters { + NamedMaximumNumberOfRegistersAutoINTEL = 0, + NamedMaximumNumberOfRegistersMax = 0x7fffffff, +}; + enum Op { OpNop = 0, OpUndef = 1, diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 index 32f209fbb..79307fd45 100644 --- a/include/spirv/unified1/spirv.hpp11 +++ b/include/spirv/unified1/spirv.hpp11 @@ -215,6 +215,9 @@ enum class ExecutionMode : unsigned { StreamingInterfaceINTEL = 6154, RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, + MaximumRegistersINTEL = 6461, + MaximumRegistersIdINTEL = 6462, + NamedMaximumRegistersINTEL = 6463, Max = 0x7fffffff, }; @@ -1225,6 +1228,7 @@ enum class Capability : unsigned { GroupUniformArithmeticKHR = 6400, MaskedGatherScatterINTEL = 6427, CacheControlsINTEL = 6441, + RegisterLimitsINTEL = 6460, Max = 0x7fffffff, }; @@ -1393,6 +1397,11 @@ enum class StoreCacheControl : unsigned { Max = 0x7fffffff, }; +enum class NamedMaximumNumberOfRegisters : unsigned { + AutoINTEL = 0, + Max = 0x7fffffff, +}; + enum class Op : unsigned { OpNop = 0, OpUndef = 1, diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json index a47a1f6ed..c329090aa 100644 --- a/include/spirv/unified1/spirv.json +++ b/include/spirv/unified1/spirv.json @@ -233,7 +233,10 @@ "FPFastMathDefault": 6028, "StreamingInterfaceINTEL": 6154, "RegisterMapInterfaceINTEL": 6160, - "NamedBarrierCountINTEL": 6417 + "NamedBarrierCountINTEL": 6417, + "MaximumRegistersINTEL": 6461, + "MaximumRegistersIdINTEL": 6462, + "NamedMaximumRegistersINTEL": 6463 } }, { @@ -1201,7 +1204,8 @@ "GlobalVariableFPGADecorationsINTEL": 6189, "GroupUniformArithmeticKHR": 6400, "MaskedGatherScatterINTEL": 6427, - "CacheControlsINTEL": 6441 + "CacheControlsINTEL": 6441, + "RegisterLimitsINTEL": 6460 } }, { @@ -1388,6 +1392,14 @@ "StreamingINTEL": 3 } }, + { + "Name": "NamedMaximumNumberOfRegisters", + "Type": "Value", + "Values": + { + "AutoINTEL": 0 + } + }, { "Name": "Op", "Type": "Value", diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua index 4a18496ed..0be8e9119 100644 --- a/include/spirv/unified1/spirv.lua +++ b/include/spirv/unified1/spirv.lua @@ -202,6 +202,9 @@ spv = { StreamingInterfaceINTEL = 6154, RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, + MaximumRegistersINTEL = 6461, + MaximumRegistersIdINTEL = 6462, + NamedMaximumRegistersINTEL = 6463, }, StorageClass = { @@ -1187,6 +1190,7 @@ spv = { GroupUniformArithmeticKHR = 6400, MaskedGatherScatterINTEL = 6427, CacheControlsINTEL = 6441, + RegisterLimitsINTEL = 6460, }, RayFlagsShift = { @@ -1337,6 +1341,10 @@ spv = { StreamingINTEL = 3, }, + NamedMaximumNumberOfRegisters = { + AutoINTEL = 0, + }, + Op = { OpNop = 0, OpUndef = 1, diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py index cac5f0627..a507f19e9 100644 --- a/include/spirv/unified1/spirv.py +++ b/include/spirv/unified1/spirv.py @@ -202,6 +202,9 @@ 'StreamingInterfaceINTEL' : 6154, 'RegisterMapInterfaceINTEL' : 6160, 'NamedBarrierCountINTEL' : 6417, + 'MaximumRegistersINTEL' : 6461, + 'MaximumRegistersIdINTEL' : 6462, + 'NamedMaximumRegistersINTEL' : 6463, }, 'StorageClass' : { @@ -1187,6 +1190,7 @@ 'GroupUniformArithmeticKHR' : 6400, 'MaskedGatherScatterINTEL' : 6427, 'CacheControlsINTEL' : 6441, + 'RegisterLimitsINTEL' : 6460, }, 'RayFlagsShift' : { @@ -1337,6 +1341,10 @@ 'StreamingINTEL' : 3, }, + 'NamedMaximumNumberOfRegisters' : { + 'AutoINTEL' : 0, + }, + 'Op' : { 'OpNop' : 0, 'OpUndef' : 1, diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d index d6cec2dbd..2ae74f5f2 100644 --- a/include/spirv/unified1/spv.d +++ b/include/spirv/unified1/spv.d @@ -214,6 +214,9 @@ enum ExecutionMode : uint StreamingInterfaceINTEL = 6154, RegisterMapInterfaceINTEL = 6160, NamedBarrierCountINTEL = 6417, + MaximumRegistersINTEL = 6461, + MaximumRegistersIdINTEL = 6462, + NamedMaximumRegistersINTEL = 6463, } enum StorageClass : uint @@ -1232,6 +1235,7 @@ enum Capability : uint GroupUniformArithmeticKHR = 6400, MaskedGatherScatterINTEL = 6427, CacheControlsINTEL = 6441, + RegisterLimitsINTEL = 6460, } enum RayFlagsShift : uint @@ -1402,6 +1406,11 @@ enum StoreCacheControl : uint StreamingINTEL = 3, } +enum NamedMaximumNumberOfRegisters : uint +{ + AutoINTEL = 0, +} + enum Op : uint { OpNop = 0, diff --git a/tools/buildHeaders/jsonToSpirv.cpp b/tools/buildHeaders/jsonToSpirv.cpp index 6eed13c13..6d140ba76 100644 --- a/tools/buildHeaders/jsonToSpirv.cpp +++ b/tools/buildHeaders/jsonToSpirv.cpp @@ -272,6 +272,7 @@ EnumValues InitializationModeQualifierParams; EnumValues HostAccessQualifierParams; EnumValues LoadCacheControlParams; EnumValues StoreCacheControlParams; +EnumValues NamedMaximumNumberOfRegistersParams; std::pair ReadFile(const std::string& path) { @@ -434,6 +435,8 @@ ClassOptionality ToOperandClassAndOptionality(const std::string& operandKind, co type = OperandLoadCacheControl; } else if (operandKind == "StoreCacheControl") { type = OperandStoreCacheControl; + } else if (operandKind == "NamedMaximumNumberOfRegisters") { + type = OperandNamedMaximumNumberOfRegisters; } if (type == OperandNone) { @@ -777,6 +780,8 @@ void jsonToSpirv(const std::string& jsonPath, bool buildingHeaders) establishOperandClass(enumName, OperandLoadCacheControl, &LoadCacheControlParams, operandEnum, category); } else if (enumName == "StoreCacheControl") { establishOperandClass(enumName, OperandStoreCacheControl, &StoreCacheControlParams, operandEnum, category); + } else if (enumName == "NamedMaximumNumberOfRegisters") { + establishOperandClass(enumName, OperandNamedMaximumNumberOfRegisters, &NamedMaximumNumberOfRegistersParams, operandEnum, category); } } diff --git a/tools/buildHeaders/jsonToSpirv.h b/tools/buildHeaders/jsonToSpirv.h index 4afbeb76f..24f75c948 100644 --- a/tools/buildHeaders/jsonToSpirv.h +++ b/tools/buildHeaders/jsonToSpirv.h @@ -103,6 +103,7 @@ enum OperandClass { OperandHostAccessQualifier, OperandLoadCacheControl, OperandStoreCacheControl, + OperandNamedMaximumNumberOfRegisters, OperandOpcode, From 8b246ff75c6615ba4532fe4fde20f1be090c3764 Mon Sep 17 00:00:00 2001 From: Rodrigo Locatti Date: Fri, 1 Mar 2024 16:06:24 -0300 Subject: [PATCH 2/6] Add SPV_NV_raw_access_chains (#417) Co-authored-by: Hans-Kristian Arntzen --- include/spirv/unified1/spirv.bf | 15 ++++++ .../spirv/unified1/spirv.core.grammar.json | 46 +++++++++++++++++++ include/spirv/unified1/spirv.cs | 15 ++++++ include/spirv/unified1/spirv.h | 15 ++++++ include/spirv/unified1/spirv.hpp | 19 ++++++++ include/spirv/unified1/spirv.hpp11 | 19 ++++++++ include/spirv/unified1/spirv.json | 11 +++++ include/spirv/unified1/spirv.lua | 13 ++++++ include/spirv/unified1/spirv.py | 13 ++++++ include/spirv/unified1/spv.d | 15 ++++++ tools/buildHeaders/jsonToSpirv.cpp | 5 ++ tools/buildHeaders/jsonToSpirv.h | 1 + 12 files changed, 187 insertions(+) diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf index c1fa60bba..92b95c876 100644 --- a/include/spirv/unified1/spirv.bf +++ b/include/spirv/unified1/spirv.bf @@ -1160,6 +1160,7 @@ namespace Spv RayQueryPositionFetchKHR = 5391, AtomicFloat16VectorNV = 5404, RayTracingDisplacementMicromapNV = 5409, + RawAccessChainsNV = 5414, SubgroupShuffleINTEL = 5568, SubgroupBufferBlockIOINTEL = 5569, SubgroupImageBlockIOINTEL = 5570, @@ -1409,6 +1410,19 @@ namespace Spv AutoINTEL = 0, } + [AllowDuplicates, CRepr] public enum RawAccessChainOperandsShift + { + RobustnessPerComponentNV = 0, + RobustnessPerElementNV = 1, + } + + [AllowDuplicates, CRepr] public enum RawAccessChainOperandsMask + { + MaskNone = 0, + RobustnessPerComponentNV = 0x00000001, + RobustnessPerElementNV = 0x00000002, + } + [AllowDuplicates, CRepr] public enum Op { OpNop = 0, @@ -1887,6 +1901,7 @@ namespace Spv OpConvertUToSampledImageNV = 5395, OpConvertSampledImageToUNV = 5396, OpSamplerImageAddressingModeNV = 5397, + OpRawAccessChainNV = 5398, OpSubgroupShuffleINTEL = 5571, OpSubgroupShuffleDownINTEL = 5572, OpSubgroupShuffleUpINTEL = 5573, diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json index ba4493352..5d904cae1 100644 --- a/include/spirv/unified1/spirv.core.grammar.json +++ b/include/spirv/unified1/spirv.core.grammar.json @@ -6251,6 +6251,24 @@ "capabilities" : [ "BindlessTextureNV" ], "version" : "None" }, + { + "opname" : "OpRawAccessChainNV", + "class" : "Memory", + "opcode" : 5398, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'Base'" }, + { "kind" : "IdRef", "name" : "'Byte stride'" }, + { "kind" : "IdRef", "name" : "'Element index'" }, + { "kind" : "IdRef", "name" : "'Byte offset'" }, + { "kind" : "RawAccessChainOperands", "quantifier" : "?" } + ], + "capabilities" : [ + "RawAccessChainsNV" + ], + "version" : "None" + }, { "opname" : "OpSubgroupShuffleINTEL", "class" : "Group", @@ -10667,6 +10685,28 @@ } ] }, + { + "category" : "BitEnum", + "kind" : "RawAccessChainOperands", + "enumerants" : [ + { + "enumerant" : "None", + "value" : "0x0000" + }, + { + "enumerant" : "RobustnessPerComponentNV", + "value" : "0x0001", + "capabilities" : [ "RawAccessChainsNV" ], + "version" : "None" + }, + { + "enumerant" : "RobustnessPerElementNV", + "value" : "0x0002", + "capabilities" : [ "RawAccessChainsNV" ], + "version" : "None" + } + ] + }, { "category" : "ValueEnum", "kind" : "SourceLanguage", @@ -16083,6 +16123,12 @@ "extensions" : [ "SPV_NV_displacement_micromap" ], "version" : "None" }, + { + "enumerant" : "RawAccessChainsNV", + "value" : 5414, + "extensions" : [ "SPV_NV_raw_access_chains" ], + "version" : "None" + }, { "enumerant" : "SubgroupShuffleINTEL", "value" : 5568, diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs index a91f4ff44..8d85cced6 100644 --- a/include/spirv/unified1/spirv.cs +++ b/include/spirv/unified1/spirv.cs @@ -1159,6 +1159,7 @@ public enum Capability RayQueryPositionFetchKHR = 5391, AtomicFloat16VectorNV = 5404, RayTracingDisplacementMicromapNV = 5409, + RawAccessChainsNV = 5414, SubgroupShuffleINTEL = 5568, SubgroupBufferBlockIOINTEL = 5569, SubgroupImageBlockIOINTEL = 5570, @@ -1408,6 +1409,19 @@ public enum NamedMaximumNumberOfRegisters AutoINTEL = 0, } + public enum RawAccessChainOperandsShift + { + RobustnessPerComponentNV = 0, + RobustnessPerElementNV = 1, + } + + public enum RawAccessChainOperandsMask + { + MaskNone = 0, + RobustnessPerComponentNV = 0x00000001, + RobustnessPerElementNV = 0x00000002, + } + public enum Op { OpNop = 0, @@ -1886,6 +1900,7 @@ public enum Op OpConvertUToSampledImageNV = 5395, OpConvertSampledImageToUNV = 5396, OpSamplerImageAddressingModeNV = 5397, + OpRawAccessChainNV = 5398, OpSubgroupShuffleINTEL = 5571, OpSubgroupShuffleDownINTEL = 5572, OpSubgroupShuffleUpINTEL = 5573, diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h index 9276b301b..e544a853d 100644 --- a/include/spirv/unified1/spirv.h +++ b/include/spirv/unified1/spirv.h @@ -1159,6 +1159,7 @@ typedef enum SpvCapability_ { SpvCapabilityRayQueryPositionFetchKHR = 5391, SpvCapabilityAtomicFloat16VectorNV = 5404, SpvCapabilityRayTracingDisplacementMicromapNV = 5409, + SpvCapabilityRawAccessChainsNV = 5414, SpvCapabilitySubgroupShuffleINTEL = 5568, SpvCapabilitySubgroupBufferBlockIOINTEL = 5569, SpvCapabilitySubgroupImageBlockIOINTEL = 5570, @@ -1406,6 +1407,18 @@ typedef enum SpvNamedMaximumNumberOfRegisters_ { SpvNamedMaximumNumberOfRegistersMax = 0x7fffffff, } SpvNamedMaximumNumberOfRegisters; +typedef enum SpvRawAccessChainOperandsShift_ { + SpvRawAccessChainOperandsRobustnessPerComponentNVShift = 0, + SpvRawAccessChainOperandsRobustnessPerElementNVShift = 1, + SpvRawAccessChainOperandsMax = 0x7fffffff, +} SpvRawAccessChainOperandsShift; + +typedef enum SpvRawAccessChainOperandsMask_ { + SpvRawAccessChainOperandsMaskNone = 0, + SpvRawAccessChainOperandsRobustnessPerComponentNVMask = 0x00000001, + SpvRawAccessChainOperandsRobustnessPerElementNVMask = 0x00000002, +} SpvRawAccessChainOperandsMask; + typedef enum SpvOp_ { SpvOpNop = 0, SpvOpUndef = 1, @@ -1883,6 +1896,7 @@ typedef enum SpvOp_ { SpvOpConvertUToSampledImageNV = 5395, SpvOpConvertSampledImageToUNV = 5396, SpvOpSamplerImageAddressingModeNV = 5397, + SpvOpRawAccessChainNV = 5398, SpvOpSubgroupShuffleINTEL = 5571, SpvOpSubgroupShuffleDownINTEL = 5572, SpvOpSubgroupShuffleUpINTEL = 5573, @@ -2617,6 +2631,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpConvertUToSampledImageNV: *hasResult = true; *hasResultType = true; break; case SpvOpConvertSampledImageToUNV: *hasResult = true; *hasResultType = true; break; case SpvOpSamplerImageAddressingModeNV: *hasResult = false; *hasResultType = false; break; + case SpvOpRawAccessChainNV: *hasResult = true; *hasResultType = true; break; case SpvOpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break; diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp index 327000af9..a383739fe 100644 --- a/include/spirv/unified1/spirv.hpp +++ b/include/spirv/unified1/spirv.hpp @@ -1155,6 +1155,7 @@ enum Capability { CapabilityRayQueryPositionFetchKHR = 5391, CapabilityAtomicFloat16VectorNV = 5404, CapabilityRayTracingDisplacementMicromapNV = 5409, + CapabilityRawAccessChainsNV = 5414, CapabilitySubgroupShuffleINTEL = 5568, CapabilitySubgroupBufferBlockIOINTEL = 5569, CapabilitySubgroupImageBlockIOINTEL = 5570, @@ -1402,6 +1403,18 @@ enum NamedMaximumNumberOfRegisters { NamedMaximumNumberOfRegistersMax = 0x7fffffff, }; +enum RawAccessChainOperandsShift { + RawAccessChainOperandsRobustnessPerComponentNVShift = 0, + RawAccessChainOperandsRobustnessPerElementNVShift = 1, + RawAccessChainOperandsMax = 0x7fffffff, +}; + +enum RawAccessChainOperandsMask { + RawAccessChainOperandsMaskNone = 0, + RawAccessChainOperandsRobustnessPerComponentNVMask = 0x00000001, + RawAccessChainOperandsRobustnessPerElementNVMask = 0x00000002, +}; + enum Op { OpNop = 0, OpUndef = 1, @@ -1879,6 +1892,7 @@ enum Op { OpConvertUToSampledImageNV = 5395, OpConvertSampledImageToUNV = 5396, OpSamplerImageAddressingModeNV = 5397, + OpRawAccessChainNV = 5398, OpSubgroupShuffleINTEL = 5571, OpSubgroupShuffleDownINTEL = 5572, OpSubgroupShuffleUpINTEL = 5573, @@ -2613,6 +2627,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case OpConvertUToSampledImageNV: *hasResult = true; *hasResultType = true; break; case OpConvertSampledImageToUNV: *hasResult = true; *hasResultType = true; break; case OpSamplerImageAddressingModeNV: *hasResult = false; *hasResultType = false; break; + case OpRawAccessChainNV: *hasResult = true; *hasResultType = true; break; case OpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break; case OpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break; case OpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break; @@ -2917,6 +2932,10 @@ inline CooperativeMatrixOperandsMask operator|(CooperativeMatrixOperandsMask a, inline CooperativeMatrixOperandsMask operator&(CooperativeMatrixOperandsMask a, CooperativeMatrixOperandsMask b) { return CooperativeMatrixOperandsMask(unsigned(a) & unsigned(b)); } inline CooperativeMatrixOperandsMask operator^(CooperativeMatrixOperandsMask a, CooperativeMatrixOperandsMask b) { return CooperativeMatrixOperandsMask(unsigned(a) ^ unsigned(b)); } inline CooperativeMatrixOperandsMask operator~(CooperativeMatrixOperandsMask a) { return CooperativeMatrixOperandsMask(~unsigned(a)); } +inline RawAccessChainOperandsMask operator|(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) | unsigned(b)); } +inline RawAccessChainOperandsMask operator&(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) & unsigned(b)); } +inline RawAccessChainOperandsMask operator^(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) ^ unsigned(b)); } +inline RawAccessChainOperandsMask operator~(RawAccessChainOperandsMask a) { return RawAccessChainOperandsMask(~unsigned(a)); } } // end namespace spv diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 index 79307fd45..d6b4fb7bc 100644 --- a/include/spirv/unified1/spirv.hpp11 +++ b/include/spirv/unified1/spirv.hpp11 @@ -1155,6 +1155,7 @@ enum class Capability : unsigned { RayQueryPositionFetchKHR = 5391, AtomicFloat16VectorNV = 5404, RayTracingDisplacementMicromapNV = 5409, + RawAccessChainsNV = 5414, SubgroupShuffleINTEL = 5568, SubgroupBufferBlockIOINTEL = 5569, SubgroupImageBlockIOINTEL = 5570, @@ -1402,6 +1403,18 @@ enum class NamedMaximumNumberOfRegisters : unsigned { Max = 0x7fffffff, }; +enum class RawAccessChainOperandsShift : unsigned { + RobustnessPerComponentNV = 0, + RobustnessPerElementNV = 1, + Max = 0x7fffffff, +}; + +enum class RawAccessChainOperandsMask : unsigned { + MaskNone = 0, + RobustnessPerComponentNV = 0x00000001, + RobustnessPerElementNV = 0x00000002, +}; + enum class Op : unsigned { OpNop = 0, OpUndef = 1, @@ -1879,6 +1892,7 @@ enum class Op : unsigned { OpConvertUToSampledImageNV = 5395, OpConvertSampledImageToUNV = 5396, OpSamplerImageAddressingModeNV = 5397, + OpRawAccessChainNV = 5398, OpSubgroupShuffleINTEL = 5571, OpSubgroupShuffleDownINTEL = 5572, OpSubgroupShuffleUpINTEL = 5573, @@ -2613,6 +2627,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { case Op::OpConvertUToSampledImageNV: *hasResult = true; *hasResultType = true; break; case Op::OpConvertSampledImageToUNV: *hasResult = true; *hasResultType = true; break; case Op::OpSamplerImageAddressingModeNV: *hasResult = false; *hasResultType = false; break; + case Op::OpRawAccessChainNV: *hasResult = true; *hasResultType = true; break; case Op::OpSubgroupShuffleINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpSubgroupShuffleDownINTEL: *hasResult = true; *hasResultType = true; break; case Op::OpSubgroupShuffleUpINTEL: *hasResult = true; *hasResultType = true; break; @@ -2917,6 +2932,10 @@ constexpr CooperativeMatrixOperandsMask operator|(CooperativeMatrixOperandsMask constexpr CooperativeMatrixOperandsMask operator&(CooperativeMatrixOperandsMask a, CooperativeMatrixOperandsMask b) { return CooperativeMatrixOperandsMask(unsigned(a) & unsigned(b)); } constexpr CooperativeMatrixOperandsMask operator^(CooperativeMatrixOperandsMask a, CooperativeMatrixOperandsMask b) { return CooperativeMatrixOperandsMask(unsigned(a) ^ unsigned(b)); } constexpr CooperativeMatrixOperandsMask operator~(CooperativeMatrixOperandsMask a) { return CooperativeMatrixOperandsMask(~unsigned(a)); } +constexpr RawAccessChainOperandsMask operator|(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) | unsigned(b)); } +constexpr RawAccessChainOperandsMask operator&(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) & unsigned(b)); } +constexpr RawAccessChainOperandsMask operator^(RawAccessChainOperandsMask a, RawAccessChainOperandsMask b) { return RawAccessChainOperandsMask(unsigned(a) ^ unsigned(b)); } +constexpr RawAccessChainOperandsMask operator~(RawAccessChainOperandsMask a) { return RawAccessChainOperandsMask(~unsigned(a)); } } // end namespace spv diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json index c329090aa..204a9c569 100644 --- a/include/spirv/unified1/spirv.json +++ b/include/spirv/unified1/spirv.json @@ -1132,6 +1132,7 @@ "RayQueryPositionFetchKHR": 5391, "AtomicFloat16VectorNV": 5404, "RayTracingDisplacementMicromapNV": 5409, + "RawAccessChainsNV": 5414, "SubgroupShuffleINTEL": 5568, "SubgroupBufferBlockIOINTEL": 5569, "SubgroupImageBlockIOINTEL": 5570, @@ -1400,6 +1401,15 @@ "AutoINTEL": 0 } }, + { + "Name": "RawAccessChainOperands", + "Type": "Bit", + "Values": + { + "RobustnessPerComponentNV": 0, + "RobustnessPerElementNV": 1 + } + }, { "Name": "Op", "Type": "Value", @@ -1881,6 +1891,7 @@ "OpConvertUToSampledImageNV": 5395, "OpConvertSampledImageToUNV": 5396, "OpSamplerImageAddressingModeNV": 5397, + "OpRawAccessChainNV": 5398, "OpSubgroupShuffleINTEL": 5571, "OpSubgroupShuffleDownINTEL": 5572, "OpSubgroupShuffleUpINTEL": 5573, diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua index 0be8e9119..6dcd1b8eb 100644 --- a/include/spirv/unified1/spirv.lua +++ b/include/spirv/unified1/spirv.lua @@ -1117,6 +1117,7 @@ spv = { RayQueryPositionFetchKHR = 5391, AtomicFloat16VectorNV = 5404, RayTracingDisplacementMicromapNV = 5409, + RawAccessChainsNV = 5414, SubgroupShuffleINTEL = 5568, SubgroupBufferBlockIOINTEL = 5569, SubgroupImageBlockIOINTEL = 5570, @@ -1345,6 +1346,17 @@ spv = { AutoINTEL = 0, }, + RawAccessChainOperandsShift = { + RobustnessPerComponentNV = 0, + RobustnessPerElementNV = 1, + }, + + RawAccessChainOperandsMask = { + MaskNone = 0, + RobustnessPerComponentNV = 0x00000001, + RobustnessPerElementNV = 0x00000002, + }, + Op = { OpNop = 0, OpUndef = 1, @@ -1822,6 +1834,7 @@ spv = { OpConvertUToSampledImageNV = 5395, OpConvertSampledImageToUNV = 5396, OpSamplerImageAddressingModeNV = 5397, + OpRawAccessChainNV = 5398, OpSubgroupShuffleINTEL = 5571, OpSubgroupShuffleDownINTEL = 5572, OpSubgroupShuffleUpINTEL = 5573, diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py index a507f19e9..4b011cfe1 100644 --- a/include/spirv/unified1/spirv.py +++ b/include/spirv/unified1/spirv.py @@ -1117,6 +1117,7 @@ 'RayQueryPositionFetchKHR' : 5391, 'AtomicFloat16VectorNV' : 5404, 'RayTracingDisplacementMicromapNV' : 5409, + 'RawAccessChainsNV' : 5414, 'SubgroupShuffleINTEL' : 5568, 'SubgroupBufferBlockIOINTEL' : 5569, 'SubgroupImageBlockIOINTEL' : 5570, @@ -1345,6 +1346,17 @@ 'AutoINTEL' : 0, }, + 'RawAccessChainOperandsShift' : { + 'RobustnessPerComponentNV' : 0, + 'RobustnessPerElementNV' : 1, + }, + + 'RawAccessChainOperandsMask' : { + 'MaskNone' : 0, + 'RobustnessPerComponentNV' : 0x00000001, + 'RobustnessPerElementNV' : 0x00000002, + }, + 'Op' : { 'OpNop' : 0, 'OpUndef' : 1, @@ -1822,6 +1834,7 @@ 'OpConvertUToSampledImageNV' : 5395, 'OpConvertSampledImageToUNV' : 5396, 'OpSamplerImageAddressingModeNV' : 5397, + 'OpRawAccessChainNV' : 5398, 'OpSubgroupShuffleINTEL' : 5571, 'OpSubgroupShuffleDownINTEL' : 5572, 'OpSubgroupShuffleUpINTEL' : 5573, diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d index 2ae74f5f2..64c115e02 100644 --- a/include/spirv/unified1/spv.d +++ b/include/spirv/unified1/spv.d @@ -1162,6 +1162,7 @@ enum Capability : uint RayQueryPositionFetchKHR = 5391, AtomicFloat16VectorNV = 5404, RayTracingDisplacementMicromapNV = 5409, + RawAccessChainsNV = 5414, SubgroupShuffleINTEL = 5568, SubgroupBufferBlockIOINTEL = 5569, SubgroupImageBlockIOINTEL = 5570, @@ -1411,6 +1412,19 @@ enum NamedMaximumNumberOfRegisters : uint AutoINTEL = 0, } +enum RawAccessChainOperandsShift : uint +{ + RobustnessPerComponentNV = 0, + RobustnessPerElementNV = 1, +} + +enum RawAccessChainOperandsMask : uint +{ + MaskNone = 0, + RobustnessPerComponentNV = 0x00000001, + RobustnessPerElementNV = 0x00000002, +} + enum Op : uint { OpNop = 0, @@ -1889,6 +1903,7 @@ enum Op : uint OpConvertUToSampledImageNV = 5395, OpConvertSampledImageToUNV = 5396, OpSamplerImageAddressingModeNV = 5397, + OpRawAccessChainNV = 5398, OpSubgroupShuffleINTEL = 5571, OpSubgroupShuffleDownINTEL = 5572, OpSubgroupShuffleUpINTEL = 5573, diff --git a/tools/buildHeaders/jsonToSpirv.cpp b/tools/buildHeaders/jsonToSpirv.cpp index 6d140ba76..34e097294 100644 --- a/tools/buildHeaders/jsonToSpirv.cpp +++ b/tools/buildHeaders/jsonToSpirv.cpp @@ -273,6 +273,7 @@ EnumValues HostAccessQualifierParams; EnumValues LoadCacheControlParams; EnumValues StoreCacheControlParams; EnumValues NamedMaximumNumberOfRegistersParams; +EnumValues RawAccessChainOperandsParams; std::pair ReadFile(const std::string& path) { @@ -437,6 +438,8 @@ ClassOptionality ToOperandClassAndOptionality(const std::string& operandKind, co type = OperandStoreCacheControl; } else if (operandKind == "NamedMaximumNumberOfRegisters") { type = OperandNamedMaximumNumberOfRegisters; + } else if (operandKind == "RawAccessChainOperands") { + type = OperandRawAccessChainOperands; } if (type == OperandNone) { @@ -782,6 +785,8 @@ void jsonToSpirv(const std::string& jsonPath, bool buildingHeaders) establishOperandClass(enumName, OperandStoreCacheControl, &StoreCacheControlParams, operandEnum, category); } else if (enumName == "NamedMaximumNumberOfRegisters") { establishOperandClass(enumName, OperandNamedMaximumNumberOfRegisters, &NamedMaximumNumberOfRegistersParams, operandEnum, category); + } else if (enumName == "RawAccessChainOperands") { + establishOperandClass(enumName, OperandRawAccessChainOperands, &RawAccessChainOperandsParams, operandEnum, category); } } diff --git a/tools/buildHeaders/jsonToSpirv.h b/tools/buildHeaders/jsonToSpirv.h index 24f75c948..c8de68f54 100644 --- a/tools/buildHeaders/jsonToSpirv.h +++ b/tools/buildHeaders/jsonToSpirv.h @@ -104,6 +104,7 @@ enum OperandClass { OperandLoadCacheControl, OperandStoreCacheControl, OperandNamedMaximumNumberOfRegisters, + OperandRawAccessChainOperands, OperandOpcode, From 04db24d69163114dacc43097a724aaab7165a5d2 Mon Sep 17 00:00:00 2001 From: PENGUINLIONG Date: Wed, 20 Mar 2024 23:38:06 +0800 Subject: [PATCH 3/6] Register spq tools for SPIR-V (#399) * Update spir-v.xml * Update spir-v.xml * Update spir-v.xml --- include/spirv/spir-v.xml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml index 4a2de8314..7a837ec25 100644 --- a/include/spirv/spir-v.xml +++ b/include/spirv/spir-v.xml @@ -92,7 +92,8 @@ - + + From 7d500c4d75ae3fbd37e1d5a20008ca9c8ee3c860 Mon Sep 17 00:00:00 2001 From: Michal Paszkowski Date: Fri, 22 Mar 2024 10:23:05 -0700 Subject: [PATCH 4/6] Register LLVM SPIR-V Backend as SPIR-V generator (#423) * Register LLVM SPIR-V Backend as SPIR-V generator * Change LLVM SPIR-V Backend vendor from "Intel" to "LLVM" --- include/spirv/spir-v.xml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml index 7a837ec25..80c1deced 100644 --- a/include/spirv/spir-v.xml +++ b/include/spirv/spir-v.xml @@ -93,7 +93,8 @@ - + + From 4f7b471f1a66b6d06462cd4ba57628cc0cd087d7 Mon Sep 17 00:00:00 2001 From: Adel Ejjeh <121976986+aejjehint@users.noreply.github.com> Date: Wed, 27 Mar 2024 10:37:11 -0500 Subject: [PATCH 5/6] Update bit reservations for loop controsl and memory operands (#424) --- include/spirv/spir-v.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml index 80c1deced..52de097a3 100644 --- a/include/spirv/spir-v.xml +++ b/include/spirv/spir-v.xml @@ -210,8 +210,8 @@ - - + + @@ -271,8 +271,8 @@ - - + + From 5e3ad389ee56fca27c9705d093ae5387ce404df4 Mon Sep 17 00:00:00 2001 From: Romaric Jodin <89833130+rjodinchr@users.noreply.github.com> Date: Tue, 23 Apr 2024 13:44:59 +0200 Subject: [PATCH 6/6] VkspReflection non-sematic: add dispatchId in configuration (#425) This is needed to add new features intercepting buffers content in vksp. --- include/spirv/unified1/NonSemanticVkspReflection.h | 2 +- .../unified1/extinst.nonsemantic.vkspreflection.grammar.json | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/include/spirv/unified1/NonSemanticVkspReflection.h b/include/spirv/unified1/NonSemanticVkspReflection.h index 0ef478a8c..331a3d95d 100644 --- a/include/spirv/unified1/NonSemanticVkspReflection.h +++ b/include/spirv/unified1/NonSemanticVkspReflection.h @@ -33,7 +33,7 @@ extern "C" { #endif enum { - NonSemanticVkspReflectionRevision = 1, + NonSemanticVkspReflectionRevision = 2, NonSemanticVkspReflectionRevision_BitWidthPadding = 0x7fffffff }; diff --git a/include/spirv/unified1/extinst.nonsemantic.vkspreflection.grammar.json b/include/spirv/unified1/extinst.nonsemantic.vkspreflection.grammar.json index bee1bea3f..379457b9e 100644 --- a/include/spirv/unified1/extinst.nonsemantic.vkspreflection.grammar.json +++ b/include/spirv/unified1/extinst.nonsemantic.vkspreflection.grammar.json @@ -1,5 +1,5 @@ { - "revision" : 1, + "revision" : 2, "instructions" : [ { "opname" : "Configuration", @@ -12,7 +12,8 @@ {"kind" : "LiteralString", "name" : "EntryPoint" }, {"kind" : "LiteralInteger", "name" : "groupCountX" }, {"kind" : "LiteralInteger", "name" : "groupCountY" }, - {"kind" : "LiteralInteger", "name" : "groupCountZ" } + {"kind" : "LiteralInteger", "name" : "groupCountZ" }, + {"kind" : "LiteralInteger", "name" : "dispatchId" } ] }, {