1.4.6

• Overhauled Flash API (breaking)
• Improved supported for output compare (including PWM output) on TIM1 and TIM8, for some variants
• Cleaned up ADC calibration code

1.4.5

• Fixed L4 and F3 targets not compiling
• Fixed USB on H7
• Fixed timer burst DMA on 32-bit timers
• Fixed an error with DMA Uart Rx
• Added support for power supply boost mode on g4
• Added channel config to UART DMA API

1.4.4

• Added EXTI clear fn
• Added SPI DMA transfer method
• Added timer burst DMA
• Added ADC DMA support for H7
• Changed DMAMUX channel alignment to DMA channels on G4
• Several PWM output fixes, including channels 2-4 being inop, and improper bit 3 output use
• Added IRDA support
• Added CRS for G4
• Fixed some G4 GPIO port bugs

1.4.2

• Added GPIO G port
• Added functions to get and set pin state without a Pin struct
• Added support for SPI4 on H7

1.4.1

• Updated Timer module to be more robust. Uses a TimerConfig struct with default, passed in the constructor that allows for additional features.
• Added TDM preset for SAI, and misc SAI tweaks
• Separated PLL source and RCC input source for H7
• Fixed a bug with embedded-HAL builds

1.3.4

• Added FIFO reception thresh, and data size cfg to SPI]
• Add SMPS power config for some H7 variants
• Remove backup domain reset on RTC init
• Added SAI code to sync between periphs and blocks
• Added support for SAI3 and 4 clock selection on H7
• Split PLL source selection from input source on H7; cleaner config separation for PLLs 1-3

1.3.3

• Added RNG module
• SAI and DFSDM use i32 signed integers
• Added customizable SAI master clock division
• Hadded flash support for H7
• Fixed a F3 GPIO port-enabling
• Updated bxcan version
• Fixed an F3/F4 HCLK speed checkbug
• Fixed max clock on F410

1.3.1

• Added RNG module
• Added customizable MCLK divider for SAI
• Fixed a bug with DFSDM divider calculation
• Use 2021 Rust edition
• Fixed an F411 clock validation bug

1.3.0

• Removed xDevice constructor parameters from most peripherals
• Fixed I2C timing bug, where high clock freqs would trigger a panic
• Updated for PAC v 0.14
• Improvements to DFSDM functionality

1.2.1

• Low power settings and USB VDD enable no longer require passing register structs
• ADC is now configured with an AdcConfig struct
• Fixed an SAI MSB/LSB bug