simulation.txt

--------------------
Cycle:1

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R1, R0, #4]
	Entry 1:[ADD	R2, R0, #1]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	0	0	0	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:2

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R4, R2, R1]
	Entry 1:[ADD	R5, R4, R2]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R1, R0, #4]
	Entry 1:[ADD	R2, R0, #1]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	0	0	0	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:3

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R4, R2, R1]
	Entry 1:[ADD	R5, R4, R2]
	Entry 2:[ADD	R6, R2, R5]
	Entry 3:[ADD	R7, R2, R6]
Pre-ALU Queue:
	Entry 0:[ADD	R2, R0, #1]
	Entry 1:
Post-ALU Buffer:[ADD	R1, R0, #4]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	0	0	0	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:4

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R4, R2, R1]
	Entry 1:[ADD	R5, R4, R2]
	Entry 2:[ADD	R6, R2, R5]
	Entry 3:[ADD	R7, R2, R6]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[ADD	R2, R0, #1]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	0	0	0	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:5

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R4, R2, R1]
	Entry 1:[ADD	R5, R4, R2]
	Entry 2:[ADD	R6, R2, R5]
	Entry 3:[ADD	R7, R2, R6]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	0	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:6

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R5, R4, R2]
	Entry 1:[ADD	R6, R2, R5]
	Entry 2:[ADD	R7, R2, R6]
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R4, R2, R1]
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	0	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:7

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R5, R4, R2]
	Entry 1:[ADD	R6, R2, R5]
	Entry 2:[ADD	R7, R2, R6]
	Entry 3:[ADD	R1, R1, R5]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[ADD	R4, R2, R1]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	0	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:8

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R5, R4, R2]
	Entry 1:[ADD	R6, R2, R5]
	Entry 2:[ADD	R7, R2, R6]
	Entry 3:[ADD	R1, R1, R5]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	5	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:9

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R2, R5]
	Entry 1:[ADD	R7, R2, R6]
	Entry 2:[ADD	R1, R1, R5]
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R5, R4, R2]
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	5	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:10

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R2, R5]
	Entry 1:[ADD	R7, R2, R6]
	Entry 2:[ADD	R1, R1, R5]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[ADD	R5, R4, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	5	0	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:11

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R2, R5]
	Entry 1:[ADD	R7, R2, R6]
	Entry 2:[ADD	R1, R1, R5]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	5	6	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:12

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R7, R2, R6]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R2, R5]
	Entry 1:[ADD	R1, R1, R5]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	5	6	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:13

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R7, R2, R6]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R1, R1, R5]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R2, R5]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	5	6	0	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:14

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R7, R2, R6]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[ADD	R1, R1, R5]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	0	5	6	7	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:15

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R7, R2, R6]
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:16

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[ADD	R7, R2, R6]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	0
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:17

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:18

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:19

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:20

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:21

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:22

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:23

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:24

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:25

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	40	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:26

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	40	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:27

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	10	1	0	5	6	7	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:28

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	10	1	0	5	1	7	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:29

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	10	1	0	1	1	7	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:30

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	1	1	1	7	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:31

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	1	1	1	7	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:32

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R4, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	1	1	1	7	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:33

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	10	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:34

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	1	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:35

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	10	0
--------------------
Cycle:36

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:37

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:38

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:39

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:40

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:41

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:42

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:43

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	40	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:44

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:45

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:46

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:47

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:48

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	9	1	1	1	1	2	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:49

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	2	1	1	2	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:50

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	2	1	1	2	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:51

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R4, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	2	1	1	2	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:52

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	9	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:53

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	1	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:54

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	9	0
--------------------
Cycle:55

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:56

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:57

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:58

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:59

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:60

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:61

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:62

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	36	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:63

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:64

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:65

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:66

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	8	1	2	1	1	3	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:67

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	8	1	2	2	1	3	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:68

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	3	2	1	3	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:69

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	3	2	1	3	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:70

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R4, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	3	2	1	3	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:71

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	8	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:72

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	1	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:73

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	8	0
--------------------
Cycle:74

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:75

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:76

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:77

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:78

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:79

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:80

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:81

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	32	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:82

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	28	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:83

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	28	2	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:84

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	7	1	3	2	1	5	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:85

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	7	1	3	2	2	5	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:86

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	7	1	3	3	2	5	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:87

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	5	3	2	5	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:88

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	5	3	2	5	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:89

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R4, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	5	3	2	5	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:90

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	7	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:91

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	6	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:92

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	7	0
--------------------
Cycle:93

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:94

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:95

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:96

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:97

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:98

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:99

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:100

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	28	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:101

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:102

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:103

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	6	1	5	3	2	8	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:104

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	6	1	5	3	3	8	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:105

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	6	1	5	5	3	8	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:106

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	8	5	3	8	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:107

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	8	5	3	8	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:108

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R4, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	8	5	3	8	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:109

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	6	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:110

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	-5	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:111

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	6	0
--------------------
Cycle:112

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:113

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:114

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:115

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:116

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:117

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:118

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:119

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	24	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:120

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:121

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:122

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	5	1	8	5	3	13	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:123

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	5	1	8	5	5	13	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:124

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	5	1	8	8	5	13	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:125

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	13	8	5	13	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:126

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	13	8	5	13	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:127

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R4, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	13	8	5	13	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:128

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	5	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:129

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	5	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:130

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	5	0
--------------------
Cycle:131

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:132

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:133

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:134

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:135

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:136

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:137

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:138

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	20	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:139

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:140

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:141

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	4	1	13	8	5	21	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:142

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	4	1	13	8	8	21	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:143

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	4	1	13	13	8	21	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:144

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:[SW	R1, 252(R0)]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	21	13	8	21	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:145

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R4, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	21	13	8	21	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:146

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R4, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	21	13	8	21	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:147

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	4	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:148

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	0
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:149

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	4	0
--------------------
Cycle:150

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:151

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:152

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:153

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:154

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:155

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:156

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:157

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	16	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:158

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	12	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:159

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	12	1	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:160

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	3	1	21	13	8	34	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:161

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	3	1	21	13	13	34	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:162

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#140
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	3	1	21	21	13	34	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:163

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	34	21	13	34	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:164

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	34	21	13	34	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:165

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R5, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	34	21	13	34	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:166

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	3	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:167

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	1	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:168

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	3	0
--------------------
Cycle:169

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:170

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:171

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:172

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:173

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:174

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:175

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:176

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	12	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:177

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:178

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:179

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	2	1	34	21	13	47	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:180

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	2	1	34	21	21	47	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:181

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#140
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	2	1	34	34	21	47	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:182

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	47	34	21	47	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:183

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	47	34	21	47	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:184

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R5, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	47	34	21	47	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:185

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	2	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:186

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	1	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:187

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	2	0
--------------------
Cycle:188

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:189

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:190

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:191

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:192

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:193

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:194

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:195

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	8	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:196

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:197

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:198

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	1	1	47	34	21	68	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:199

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	1	1	47	34	34	68	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:200

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#140
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	1	1	47	47	34	68	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:201

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	68	47	34	68	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:202

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	68	47	34	68	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:203

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R5, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	68	47	34	68	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:204

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	1	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:205

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	2	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:206

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	1	0
--------------------
Cycle:207

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:208

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:209

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:210

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:211

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:[LW	R5, 188(R10)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:212

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:213

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:[SRL	R11, R1, #2]
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SLL	R10, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:214

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:[SLL	R10, R1, #2]
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	4	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:215

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
	Entry 2:[LW	R3, 180(R10)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:[SRL	R11, R1, #2]
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:216

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:[SRL	R11, R1, #2]
Pre-MEM Queue:
	Entry 0:[LW	R5, 188(R10)]
	Entry 1:[LW	R4, 184(R10)]
Post-MEM Buffer:

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:217

IF Unit:
	Waiting Instruction: BGTZ	R11, #8
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R4, 184(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R5, 188(R10)]

Registers
R00:	0	0	1	68	47	34	102	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:218

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BGTZ	R11, #8
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R3, 180(R10)]
	Entry 1:
Post-MEM Buffer:[LW	R4, 184(R10)]

Registers
R00:	0	0	1	68	47	47	102	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:219

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#140
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R3, 180(R10)]

Registers
R00:	0	0	1	68	68	47	102	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:220

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:[SW	R6, 176(R10)]
	Entry 2:[SUB	R1, R1, R2]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	102	68	47	102	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:221

IF Unit:
	Waiting Instruction: 
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[ADD	R6, R5, R3]
	Entry 1:[SUB	R1, R1, R2]
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	102	68	47	102	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:222

IF Unit:
	Waiting Instruction: 
	Executed Instruction: J	#96
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:[SUB	R1, R1, R2]
	Entry 1:
Post-ALU Buffer:[ADD	R6, R5, R3]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	102	68	47	102	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:223

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:[SW	R1, 252(R0)]
	Entry 2:[LW	R1, 252(R0)]
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:[SUB	R1, R1, R2]
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	0	1	102	68	47	149	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:224

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:[LW	R1, 252(R0)]
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R6, 176(R10)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	-1	1	102	68	47	149	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	1	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:225

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[SW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	-1	1	102	68	47	149	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	149	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	0	0
--------------------
Cycle:226

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:[LW	R1, 252(R0)]
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	-1	1	102	68	47	149	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	149	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	-1	0
--------------------
Cycle:227

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:[LW	R1, 252(R0)]

Registers
R00:	0	-1	1	102	68	47	149	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	149	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	-1	0
--------------------
Cycle:228

IF Unit:
	Waiting Instruction: BLTZ	R1, #52
	Executed Instruction: 
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	-1	1	102	68	47	149	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	149	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	-1	0
--------------------
Cycle:229

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BLTZ	R1, #52
Pre-Issue Buffer:
	Entry 0:
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	-1	1	102	68	47	149	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	149	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	-1	0
--------------------
Cycle:230

IF Unit:
	Waiting Instruction: 
	Executed Instruction: BREAK
Pre-Issue Buffer:
	Entry 0:[ADD	R1, R0, #4]
	Entry 1:
	Entry 2:
	Entry 3:
Pre-ALU Queue:
	Entry 0:
	Entry 1:
Post-ALU Buffer:
Pre-ALUB Queue:
	Entry 0:
	Entry 1:
Post-ALUB Buffer:
Pre-MEM Queue:
	Entry 0:
	Entry 1:
Post-MEM Buffer:

Registers
R00:	0	-1	1	102	68	47	149	8
R08:	0	0	0	0	0	0	0	0
R16:	0	0	0	0	0	0	0	0
R24:	0	0	0	0	0	0	0	0

Data
164:	0	-1	0	149	102	68	47	34
196:	21	13	8	5	3	2	1	1
228:	1	1	1	1	1	1	-1	0