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info.yaml
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# Tiny Tapeout project information
project:
title: "CEJMU Beers and Adders" # Project title
author: "Prof. Dr.-Ing. Matthias Jung, Philipp Wetzstein, Derek Christ, Jonathan Hager" # Your name
discord: "myzinsky" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "Several projects to show in lectures. Includes a simple state-machine, a decoder and two 24 bit adders. Refer to documentation for details" # One line description of what your project does
language: "SystemVerilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 12000000 # Clock frequency in Hz (or 0 if not applicable)
# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
# Your top module name must start with "tt_um_". Make it unique by including your github username:
top_module: "tt_um_cejmu"
# List your project's source files here.
# Source files must be in ./src and you must list each source file separately, one per line.
# Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
source_files:
- "tt_um_cejmu.v"
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: "Multiplexed to all designs (refer to documentation for details)"
ui[1]: "..."
ui[2]: "..."
ui[3]: "..."
ui[4]: "..."
ui[5]: "..."
ui[6]: "..."
ui[7]: "..."
# Outputs
uo[0]: "Multiplexed from all designs (refer to documentation for details)"
uo[1]: "..."
uo[2]: "..."
uo[3]: "..."
uo[4]: "..."
uo[5]: "..."
uo[6]: "..."
uo[7]: "..."
# Bidirectional pins
uio[0]: "Select design (input)"
uio[1]: "Select design (input)"
uio[2]: "start_calc"
uio[3]: "output_result"
uio[4]: "unused"
uio[5]: "unused"
uio[6]: "overflow bit of RCA (output)"
uio[7]: "overflow bit of CLA (output)"
# Do not change!
yaml_version: 6