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timing_report.txt
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timing_report.txt
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (win64) Build 3526262 Mon Apr 18 15:48:16 MDT 2022
| Date : Wed Oct 18 11:04:51 2023
| Host : DESKTOP-Q9FPE3B running 64-bit major release (build 9200)
| Command : report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 -file C:/Users/richardhsu/soc-lab3-syn/timing_report.txt
| Design : fir
| Device : 7z020-clg400
| Speed File : -1 PRODUCTION 1.12 2019-11-22
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------
No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (159)
6. checking no_output_delay (166)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay (159)
--------------------------------
There are 159 input ports with no input delay specified. (HIGH)
araddr[0]
araddr[10]
araddr[11]
araddr[1]
araddr[2]
araddr[3]
araddr[4]
araddr[5]
araddr[6]
araddr[7]
araddr[8]
araddr[9]
arvalid
awaddr[0]
awaddr[10]
awaddr[11]
awaddr[1]
awaddr[2]
awaddr[3]
awaddr[4]
awaddr[5]
awaddr[6]
awaddr[7]
awaddr[8]
awaddr[9]
awvalid
axis_rst_n
data_Do[0]
data_Do[10]
data_Do[11]
data_Do[12]
data_Do[13]
data_Do[14]
data_Do[15]
data_Do[16]
data_Do[17]
data_Do[18]
data_Do[19]
data_Do[1]
data_Do[20]
data_Do[21]
data_Do[22]
data_Do[23]
data_Do[24]
data_Do[25]
data_Do[26]
data_Do[27]
data_Do[28]
data_Do[29]
data_Do[2]
data_Do[30]
data_Do[31]
data_Do[3]
data_Do[4]
data_Do[5]
data_Do[6]
data_Do[7]
data_Do[8]
data_Do[9]
rready
sm_tready
ss_tdata[0]
ss_tdata[10]
ss_tdata[11]
ss_tdata[12]
ss_tdata[13]
ss_tdata[14]
ss_tdata[15]
ss_tdata[16]
ss_tdata[17]
ss_tdata[18]
ss_tdata[19]
ss_tdata[1]
ss_tdata[20]
ss_tdata[21]
ss_tdata[22]
ss_tdata[23]
ss_tdata[24]
ss_tdata[25]
ss_tdata[26]
ss_tdata[27]
ss_tdata[28]
ss_tdata[29]
ss_tdata[2]
ss_tdata[30]
ss_tdata[31]
ss_tdata[3]
ss_tdata[4]
ss_tdata[5]
ss_tdata[6]
ss_tdata[7]
ss_tdata[8]
ss_tdata[9]
ss_tvalid
tap_Do[0]
tap_Do[10]
tap_Do[11]
tap_Do[12]
tap_Do[13]
tap_Do[14]
tap_Do[15]
tap_Do[16]
tap_Do[17]
tap_Do[18]
tap_Do[19]
tap_Do[1]
tap_Do[20]
tap_Do[21]
tap_Do[22]
tap_Do[23]
tap_Do[24]
tap_Do[25]
tap_Do[26]
tap_Do[27]
tap_Do[28]
tap_Do[29]
tap_Do[2]
tap_Do[30]
tap_Do[31]
tap_Do[3]
tap_Do[4]
tap_Do[5]
tap_Do[6]
tap_Do[7]
tap_Do[8]
tap_Do[9]
wdata[0]
wdata[10]
wdata[11]
wdata[12]
wdata[13]
wdata[14]
wdata[15]
wdata[16]
wdata[17]
wdata[18]
wdata[19]
wdata[1]
wdata[20]
wdata[21]
wdata[22]
wdata[23]
wdata[24]
wdata[25]
wdata[26]
wdata[27]
wdata[28]
wdata[29]
wdata[2]
wdata[30]
wdata[31]
wdata[3]
wdata[4]
wdata[5]
wdata[6]
wdata[7]
wdata[8]
wdata[9]
wvalid
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (166)
---------------------------------
There are 166 ports with no output delay specified. (HIGH)
arready
awready
data_A[10]
data_A[11]
data_A[2]
data_A[3]
data_A[4]
data_A[5]
data_A[6]
data_A[7]
data_A[8]
data_A[9]
data_Di[0]
data_Di[10]
data_Di[11]
data_Di[12]
data_Di[13]
data_Di[14]
data_Di[15]
data_Di[16]
data_Di[17]
data_Di[18]
data_Di[19]
data_Di[1]
data_Di[20]
data_Di[21]
data_Di[22]
data_Di[23]
data_Di[24]
data_Di[25]
data_Di[26]
data_Di[27]
data_Di[28]
data_Di[29]
data_Di[2]
data_Di[30]
data_Di[31]
data_Di[3]
data_Di[4]
data_Di[5]
data_Di[6]
data_Di[7]
data_Di[8]
data_Di[9]
data_EN
data_WE[0]
data_WE[1]
data_WE[2]
data_WE[3]
rdata[0]
rdata[10]
rdata[11]
rdata[12]
rdata[13]
rdata[14]
rdata[15]
rdata[16]
rdata[17]
rdata[18]
rdata[19]
rdata[1]
rdata[20]
rdata[21]
rdata[22]
rdata[23]
rdata[24]
rdata[25]
rdata[26]
rdata[27]
rdata[28]
rdata[29]
rdata[2]
rdata[30]
rdata[31]
rdata[3]
rdata[4]
rdata[5]
rdata[6]
rdata[7]
rdata[8]
rdata[9]
rvalid
sm_tdata[0]
sm_tdata[10]
sm_tdata[11]
sm_tdata[12]
sm_tdata[13]
sm_tdata[14]
sm_tdata[15]
sm_tdata[16]
sm_tdata[17]
sm_tdata[18]
sm_tdata[19]
sm_tdata[1]
sm_tdata[20]
sm_tdata[21]
sm_tdata[22]
sm_tdata[23]
sm_tdata[24]
sm_tdata[25]
sm_tdata[26]
sm_tdata[27]
sm_tdata[28]
sm_tdata[29]
sm_tdata[2]
sm_tdata[30]
sm_tdata[31]
sm_tdata[3]
sm_tdata[4]
sm_tdata[5]
sm_tdata[6]
sm_tdata[7]
sm_tdata[8]
sm_tdata[9]
sm_tlast
sm_tvalid
ss_tready
tap_A[0]
tap_A[10]
tap_A[11]
tap_A[1]
tap_A[2]
tap_A[3]
tap_A[4]
tap_A[5]
tap_A[6]
tap_A[7]
tap_A[8]
tap_A[9]
tap_Di[0]
tap_Di[10]
tap_Di[11]
tap_Di[12]
tap_Di[13]
tap_Di[14]
tap_Di[15]
tap_Di[16]
tap_Di[17]
tap_Di[18]
tap_Di[19]
tap_Di[1]
tap_Di[20]
tap_Di[21]
tap_Di[22]
tap_Di[23]
tap_Di[24]
tap_Di[25]
tap_Di[26]
tap_Di[27]
tap_Di[28]
tap_Di[29]
tap_Di[2]
tap_Di[30]
tap_Di[31]
tap_Di[3]
tap_Di[4]
tap_Di[5]
tap_Di[6]
tap_Di[7]
tap_Di[8]
tap_Di[9]
tap_WE[0]
tap_WE[1]
tap_WE[2]
tap_WE[3]
wready
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
1.261 0.000 0 388 0.147 0.000 0 388 7.000 0.000 0 279
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
axis_clk {0.000 7.500} 15.000 66.667
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
axis_clk 1.261 0.000 0 388 0.147 0.000 0 388 7.000 0.000 0 279
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock
---------- ---------- --------
(none) axis_clk
(none) axis_clk
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: axis_clk
To Clock: axis_clk
Setup : 0 Failing Endpoints, Worst Slack 1.261ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.147ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.261ns (required time - arrival time)
Source: data_length_reg[1]/C
(rising edge-triggered cell FDCE clocked by axis_clk {[email protected] [email protected] period=15.000ns})
Destination: accumulated_result_reg[29]/D
(rising edge-triggered cell FDCE clocked by axis_clk {[email protected] [email protected] period=15.000ns})
Path Group: axis_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 15.000ns (axis_clk [email protected] - axis_clk [email protected])
Data Path Delay: 13.634ns (logic 9.575ns (70.227%) route 4.059ns (29.773%))
Logic Levels: 15 (CARRY4=9 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 17.128 - 15.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axis_clk rise edge)
0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r axis_clk_IBUF_BUFG_inst/O
net (fo=278, unplaced) 0.584 2.456 axis_clk_IBUF_BUFG
FDCE r data_length_reg[1]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.934 f data_length_reg[1]/Q
net (fo=5, unplaced) 0.769 3.703 data_length[1]
f data_Di_OBUF[31]_inst_i_23/I1
LUT4 (Prop_lut4_I1_O) 0.319 4.022 r data_Di_OBUF[31]_inst_i_23/O
net (fo=1, unplaced) 0.000 4.022 data_Di_OBUF[31]_inst_i_23_n_0
r data_Di_OBUF[31]_inst_i_14/DI[0]
CARRY4 (Prop_carry4_DI[0]_CO[3])
0.576 4.598 r data_Di_OBUF[31]_inst_i_14/CO[3]
net (fo=1, unplaced) 0.009 4.607 data_Di_OBUF[31]_inst_i_14_n_0
r data_Di_OBUF[31]_inst_i_9/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.724 r data_Di_OBUF[31]_inst_i_9/CO[3]
net (fo=1, unplaced) 0.000 4.724 data_Di_OBUF[31]_inst_i_9_n_0
r data_Di_OBUF[31]_inst_i_4/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.841 r data_Di_OBUF[31]_inst_i_4/CO[3]
net (fo=1, unplaced) 0.000 4.841 data_Di_OBUF[31]_inst_i_4_n_0
r data_Di_OBUF[31]_inst_i_2/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.958 f data_Di_OBUF[31]_inst_i_2/CO[3]
net (fo=32, unplaced) 0.989 5.947 mult11
f data_Di_OBUF[16]_inst_i_1/I1
LUT5 (Prop_lut5_I1_O) 0.124 6.071 r data_Di_OBUF[16]_inst_i_1/O
net (fo=3, unplaced) 0.800 6.871 data_Di_OBUF[16]
r mult_result__0/A[16]
DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47])
4.036 10.907 r mult_result__0/PCOUT[47]
net (fo=1, unplaced) 0.055 10.962 mult_result__0_n_106
r mult_result__1/PCIN[47]
DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
1.518 12.480 r mult_result__1/P[0]
net (fo=2, unplaced) 0.800 13.280 mult_result__1_n_105
r accumulated_result[16]_i_13/I0
LUT2 (Prop_lut2_I0_O) 0.124 13.404 r accumulated_result[16]_i_13/O
net (fo=1, unplaced) 0.000 13.404 accumulated_result[16]_i_13_n_0
r accumulated_result_reg[16]_i_10/S[1]
CARRY4 (Prop_carry4_S[1]_CO[3])
0.533 13.937 r accumulated_result_reg[16]_i_10/CO[3]
net (fo=1, unplaced) 0.009 13.946 accumulated_result_reg[16]_i_10_n_0
r accumulated_result_reg[20]_i_10/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 14.063 r accumulated_result_reg[20]_i_10/CO[3]
net (fo=1, unplaced) 0.000 14.063 accumulated_result_reg[20]_i_10_n_0
r accumulated_result_reg[24]_i_10/CI
CARRY4 (Prop_carry4_CI_O[3])
0.331 14.394 r accumulated_result_reg[24]_i_10/O[3]
net (fo=2, unplaced) 0.629 15.023 mult_result__3[27]
r accumulated_result[24]_i_2/I0
LUT3 (Prop_lut3_I0_O) 0.302 15.325 r accumulated_result[24]_i_2/O
net (fo=1, unplaced) 0.000 15.325 accumulated_result[24]_i_2_n_0
r accumulated_result_reg[24]_i_1/DI[3]
CARRY4 (Prop_carry4_DI[3]_CO[3])
0.429 15.754 r accumulated_result_reg[24]_i_1/CO[3]
net (fo=1, unplaced) 0.000 15.754 accumulated_result_reg[24]_i_1_n_0
r accumulated_result_reg[28]_i_1/CI
CARRY4 (Prop_carry4_CI_O[1])
0.337 16.091 r accumulated_result_reg[28]_i_1/O[1]
net (fo=1, unplaced) 0.000 16.091 accumulated_result_reg[28]_i_1_n_6
FDCE r accumulated_result_reg[29]/D
------------------------------------------------------------------- -------------------
(clock axis_clk rise edge)
15.000 15.000 r
0.000 15.000 r axis_clk (IN)
net (fo=0) 0.000 15.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 15.838 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.760 16.598 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 16.689 r axis_clk_IBUF_BUFG_inst/O
net (fo=278, unplaced) 0.439 17.128 axis_clk_IBUF_BUFG
FDCE r accumulated_result_reg[29]/C
clock pessimism 0.184 17.311
clock uncertainty -0.035 17.276
FDCE (Setup_fdce_C_D) 0.076 17.352 accumulated_result_reg[29]
-------------------------------------------------------------------
required time 17.352
arrival time -16.091
-------------------------------------------------------------------
slack 1.261
Slack (MET) : 1.267ns (required time - arrival time)
Source: data_length_reg[1]/C
(rising edge-triggered cell FDCE clocked by axis_clk {[email protected] [email protected] period=15.000ns})
Destination: accumulated_result_reg[31]/D
(rising edge-triggered cell FDCE clocked by axis_clk {[email protected] [email protected] period=15.000ns})
Path Group: axis_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 15.000ns (axis_clk [email protected] - axis_clk [email protected])
Data Path Delay: 13.628ns (logic 9.569ns (70.214%) route 4.059ns (29.786%))
Logic Levels: 15 (CARRY4=9 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 17.128 - 15.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axis_clk rise edge)
0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r axis_clk_IBUF_BUFG_inst/O
net (fo=278, unplaced) 0.584 2.456 axis_clk_IBUF_BUFG
FDCE r data_length_reg[1]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.934 f data_length_reg[1]/Q
net (fo=5, unplaced) 0.769 3.703 data_length[1]
f data_Di_OBUF[31]_inst_i_23/I1
LUT4 (Prop_lut4_I1_O) 0.319 4.022 r data_Di_OBUF[31]_inst_i_23/O
net (fo=1, unplaced) 0.000 4.022 data_Di_OBUF[31]_inst_i_23_n_0
r data_Di_OBUF[31]_inst_i_14/DI[0]
CARRY4 (Prop_carry4_DI[0]_CO[3])
0.576 4.598 r data_Di_OBUF[31]_inst_i_14/CO[3]
net (fo=1, unplaced) 0.009 4.607 data_Di_OBUF[31]_inst_i_14_n_0
r data_Di_OBUF[31]_inst_i_9/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.724 r data_Di_OBUF[31]_inst_i_9/CO[3]
net (fo=1, unplaced) 0.000 4.724 data_Di_OBUF[31]_inst_i_9_n_0
r data_Di_OBUF[31]_inst_i_4/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.841 r data_Di_OBUF[31]_inst_i_4/CO[3]
net (fo=1, unplaced) 0.000 4.841 data_Di_OBUF[31]_inst_i_4_n_0
r data_Di_OBUF[31]_inst_i_2/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.958 f data_Di_OBUF[31]_inst_i_2/CO[3]
net (fo=32, unplaced) 0.989 5.947 mult11
f data_Di_OBUF[16]_inst_i_1/I1
LUT5 (Prop_lut5_I1_O) 0.124 6.071 r data_Di_OBUF[16]_inst_i_1/O
net (fo=3, unplaced) 0.800 6.871 data_Di_OBUF[16]
r mult_result__0/A[16]
DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47])
4.036 10.907 r mult_result__0/PCOUT[47]
net (fo=1, unplaced) 0.055 10.962 mult_result__0_n_106
r mult_result__1/PCIN[47]
DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
1.518 12.480 r mult_result__1/P[0]
net (fo=2, unplaced) 0.800 13.280 mult_result__1_n_105
r accumulated_result[16]_i_13/I0
LUT2 (Prop_lut2_I0_O) 0.124 13.404 r accumulated_result[16]_i_13/O
net (fo=1, unplaced) 0.000 13.404 accumulated_result[16]_i_13_n_0
r accumulated_result_reg[16]_i_10/S[1]
CARRY4 (Prop_carry4_S[1]_CO[3])
0.533 13.937 r accumulated_result_reg[16]_i_10/CO[3]
net (fo=1, unplaced) 0.009 13.946 accumulated_result_reg[16]_i_10_n_0
r accumulated_result_reg[20]_i_10/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 14.063 r accumulated_result_reg[20]_i_10/CO[3]
net (fo=1, unplaced) 0.000 14.063 accumulated_result_reg[20]_i_10_n_0
r accumulated_result_reg[24]_i_10/CI
CARRY4 (Prop_carry4_CI_O[3])
0.331 14.394 r accumulated_result_reg[24]_i_10/O[3]
net (fo=2, unplaced) 0.629 15.023 mult_result__3[27]
r accumulated_result[24]_i_2/I0
LUT3 (Prop_lut3_I0_O) 0.302 15.325 r accumulated_result[24]_i_2/O
net (fo=1, unplaced) 0.000 15.325 accumulated_result[24]_i_2_n_0
r accumulated_result_reg[24]_i_1/DI[3]
CARRY4 (Prop_carry4_DI[3]_CO[3])
0.429 15.754 r accumulated_result_reg[24]_i_1/CO[3]
net (fo=1, unplaced) 0.000 15.754 accumulated_result_reg[24]_i_1_n_0
r accumulated_result_reg[28]_i_1/CI
CARRY4 (Prop_carry4_CI_O[3])
0.331 16.085 r accumulated_result_reg[28]_i_1/O[3]
net (fo=1, unplaced) 0.000 16.085 accumulated_result_reg[28]_i_1_n_4
FDCE r accumulated_result_reg[31]/D
------------------------------------------------------------------- -------------------
(clock axis_clk rise edge)
15.000 15.000 r
0.000 15.000 r axis_clk (IN)
net (fo=0) 0.000 15.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 15.838 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.760 16.598 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 16.689 r axis_clk_IBUF_BUFG_inst/O
net (fo=278, unplaced) 0.439 17.128 axis_clk_IBUF_BUFG
FDCE r accumulated_result_reg[31]/C
clock pessimism 0.184 17.311
clock uncertainty -0.035 17.276
FDCE (Setup_fdce_C_D) 0.076 17.352 accumulated_result_reg[31]
-------------------------------------------------------------------
required time 17.352
arrival time -16.085
-------------------------------------------------------------------
slack 1.267
Slack (MET) : 1.342ns (required time - arrival time)
Source: data_length_reg[1]/C
(rising edge-triggered cell FDCE clocked by axis_clk {[email protected] [email protected] period=15.000ns})
Destination: accumulated_result_reg[30]/D
(rising edge-triggered cell FDCE clocked by axis_clk {[email protected] [email protected] period=15.000ns})
Path Group: axis_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 15.000ns (axis_clk [email protected] - axis_clk [email protected])
Data Path Delay: 13.553ns (logic 9.494ns (70.049%) route 4.059ns (29.951%))
Logic Levels: 15 (CARRY4=9 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 17.128 - 15.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axis_clk rise edge)
0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r axis_clk_IBUF_BUFG_inst/O
net (fo=278, unplaced) 0.584 2.456 axis_clk_IBUF_BUFG
FDCE r data_length_reg[1]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.934 f data_length_reg[1]/Q
net (fo=5, unplaced) 0.769 3.703 data_length[1]
f data_Di_OBUF[31]_inst_i_23/I1
LUT4 (Prop_lut4_I1_O) 0.319 4.022 r data_Di_OBUF[31]_inst_i_23/O
net (fo=1, unplaced) 0.000 4.022 data_Di_OBUF[31]_inst_i_23_n_0
r data_Di_OBUF[31]_inst_i_14/DI[0]
CARRY4 (Prop_carry4_DI[0]_CO[3])
0.576 4.598 r data_Di_OBUF[31]_inst_i_14/CO[3]
net (fo=1, unplaced) 0.009 4.607 data_Di_OBUF[31]_inst_i_14_n_0
r data_Di_OBUF[31]_inst_i_9/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.724 r data_Di_OBUF[31]_inst_i_9/CO[3]
net (fo=1, unplaced) 0.000 4.724 data_Di_OBUF[31]_inst_i_9_n_0
r data_Di_OBUF[31]_inst_i_4/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.841 r data_Di_OBUF[31]_inst_i_4/CO[3]
net (fo=1, unplaced) 0.000 4.841 data_Di_OBUF[31]_inst_i_4_n_0
r data_Di_OBUF[31]_inst_i_2/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.958 f data_Di_OBUF[31]_inst_i_2/CO[3]
net (fo=32, unplaced) 0.989 5.947 mult11
f data_Di_OBUF[16]_inst_i_1/I1
LUT5 (Prop_lut5_I1_O) 0.124 6.071 r data_Di_OBUF[16]_inst_i_1/O
net (fo=3, unplaced) 0.800 6.871 data_Di_OBUF[16]
r mult_result__0/A[16]
DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47])
4.036 10.907 r mult_result__0/PCOUT[47]
net (fo=1, unplaced) 0.055 10.962 mult_result__0_n_106
r mult_result__1/PCIN[47]
DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
1.518 12.480 r mult_result__1/P[0]
net (fo=2, unplaced) 0.800 13.280 mult_result__1_n_105
r accumulated_result[16]_i_13/I0
LUT2 (Prop_lut2_I0_O) 0.124 13.404 r accumulated_result[16]_i_13/O
net (fo=1, unplaced) 0.000 13.404 accumulated_result[16]_i_13_n_0
r accumulated_result_reg[16]_i_10/S[1]
CARRY4 (Prop_carry4_S[1]_CO[3])
0.533 13.937 r accumulated_result_reg[16]_i_10/CO[3]
net (fo=1, unplaced) 0.009 13.946 accumulated_result_reg[16]_i_10_n_0
r accumulated_result_reg[20]_i_10/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 14.063 r accumulated_result_reg[20]_i_10/CO[3]
net (fo=1, unplaced) 0.000 14.063 accumulated_result_reg[20]_i_10_n_0
r accumulated_result_reg[24]_i_10/CI
CARRY4 (Prop_carry4_CI_O[3])
0.331 14.394 r accumulated_result_reg[24]_i_10/O[3]
net (fo=2, unplaced) 0.629 15.023 mult_result__3[27]
r accumulated_result[24]_i_2/I0
LUT3 (Prop_lut3_I0_O) 0.302 15.325 r accumulated_result[24]_i_2/O
net (fo=1, unplaced) 0.000 15.325 accumulated_result[24]_i_2_n_0
r accumulated_result_reg[24]_i_1/DI[3]
CARRY4 (Prop_carry4_DI[3]_CO[3])
0.429 15.754 r accumulated_result_reg[24]_i_1/CO[3]
net (fo=1, unplaced) 0.000 15.754 accumulated_result_reg[24]_i_1_n_0
r accumulated_result_reg[28]_i_1/CI
CARRY4 (Prop_carry4_CI_O[2])
0.256 16.010 r accumulated_result_reg[28]_i_1/O[2]
net (fo=1, unplaced) 0.000 16.010 accumulated_result_reg[28]_i_1_n_5
FDCE r accumulated_result_reg[30]/D
------------------------------------------------------------------- -------------------
(clock axis_clk rise edge)
15.000 15.000 r
0.000 15.000 r axis_clk (IN)
net (fo=0) 0.000 15.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 15.838 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.760 16.598 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 16.689 r axis_clk_IBUF_BUFG_inst/O
net (fo=278, unplaced) 0.439 17.128 axis_clk_IBUF_BUFG
FDCE r accumulated_result_reg[30]/C
clock pessimism 0.184 17.311
clock uncertainty -0.035 17.276
FDCE (Setup_fdce_C_D) 0.076 17.352 accumulated_result_reg[30]
-------------------------------------------------------------------
required time 17.352
arrival time -16.010
-------------------------------------------------------------------
slack 1.342
Slack (MET) : 1.366ns (required time - arrival time)
Source: data_length_reg[1]/C
(rising edge-triggered cell FDCE clocked by axis_clk {[email protected] [email protected] period=15.000ns})
Destination: accumulated_result_reg[28]/D
(rising edge-triggered cell FDCE clocked by axis_clk {[email protected] [email protected] period=15.000ns})
Path Group: axis_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 15.000ns (axis_clk [email protected] - axis_clk [email protected])
Data Path Delay: 13.529ns (logic 9.470ns (69.996%) route 4.059ns (30.004%))
Logic Levels: 15 (CARRY4=9 DSP48E1=2 LUT2=1 LUT3=1 LUT4=1 LUT5=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 2.128ns = ( 17.128 - 15.000 )
Source Clock Delay (SCD): 2.456ns
Clock Pessimism Removal (CPR): 0.184ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axis_clk rise edge)
0.000 0.000 r
0.000 0.000 r axis_clk (IN)
net (fo=0) 0.000 0.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.972 0.972 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.800 1.771 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.101 1.872 r axis_clk_IBUF_BUFG_inst/O
net (fo=278, unplaced) 0.584 2.456 axis_clk_IBUF_BUFG
FDCE r data_length_reg[1]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.478 2.934 f data_length_reg[1]/Q
net (fo=5, unplaced) 0.769 3.703 data_length[1]
f data_Di_OBUF[31]_inst_i_23/I1
LUT4 (Prop_lut4_I1_O) 0.319 4.022 r data_Di_OBUF[31]_inst_i_23/O
net (fo=1, unplaced) 0.000 4.022 data_Di_OBUF[31]_inst_i_23_n_0
r data_Di_OBUF[31]_inst_i_14/DI[0]
CARRY4 (Prop_carry4_DI[0]_CO[3])
0.576 4.598 r data_Di_OBUF[31]_inst_i_14/CO[3]
net (fo=1, unplaced) 0.009 4.607 data_Di_OBUF[31]_inst_i_14_n_0
r data_Di_OBUF[31]_inst_i_9/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.724 r data_Di_OBUF[31]_inst_i_9/CO[3]
net (fo=1, unplaced) 0.000 4.724 data_Di_OBUF[31]_inst_i_9_n_0
r data_Di_OBUF[31]_inst_i_4/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.841 r data_Di_OBUF[31]_inst_i_4/CO[3]
net (fo=1, unplaced) 0.000 4.841 data_Di_OBUF[31]_inst_i_4_n_0
r data_Di_OBUF[31]_inst_i_2/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 4.958 f data_Di_OBUF[31]_inst_i_2/CO[3]
net (fo=32, unplaced) 0.989 5.947 mult11
f data_Di_OBUF[16]_inst_i_1/I1
LUT5 (Prop_lut5_I1_O) 0.124 6.071 r data_Di_OBUF[16]_inst_i_1/O
net (fo=3, unplaced) 0.800 6.871 data_Di_OBUF[16]
r mult_result__0/A[16]
DSP48E1 (Prop_dsp48e1_A[16]_PCOUT[47])
4.036 10.907 r mult_result__0/PCOUT[47]
net (fo=1, unplaced) 0.055 10.962 mult_result__0_n_106
r mult_result__1/PCIN[47]
DSP48E1 (Prop_dsp48e1_PCIN[47]_P[0])
1.518 12.480 r mult_result__1/P[0]
net (fo=2, unplaced) 0.800 13.280 mult_result__1_n_105
r accumulated_result[16]_i_13/I0
LUT2 (Prop_lut2_I0_O) 0.124 13.404 r accumulated_result[16]_i_13/O
net (fo=1, unplaced) 0.000 13.404 accumulated_result[16]_i_13_n_0
r accumulated_result_reg[16]_i_10/S[1]
CARRY4 (Prop_carry4_S[1]_CO[3])
0.533 13.937 r accumulated_result_reg[16]_i_10/CO[3]
net (fo=1, unplaced) 0.009 13.946 accumulated_result_reg[16]_i_10_n_0
r accumulated_result_reg[20]_i_10/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.117 14.063 r accumulated_result_reg[20]_i_10/CO[3]
net (fo=1, unplaced) 0.000 14.063 accumulated_result_reg[20]_i_10_n_0
r accumulated_result_reg[24]_i_10/CI
CARRY4 (Prop_carry4_CI_O[3])
0.331 14.394 r accumulated_result_reg[24]_i_10/O[3]
net (fo=2, unplaced) 0.629 15.023 mult_result__3[27]
r accumulated_result[24]_i_2/I0
LUT3 (Prop_lut3_I0_O) 0.302 15.325 r accumulated_result[24]_i_2/O
net (fo=1, unplaced) 0.000 15.325 accumulated_result[24]_i_2_n_0
r accumulated_result_reg[24]_i_1/DI[3]
CARRY4 (Prop_carry4_DI[3]_CO[3])
0.429 15.754 r accumulated_result_reg[24]_i_1/CO[3]
net (fo=1, unplaced) 0.000 15.754 accumulated_result_reg[24]_i_1_n_0
r accumulated_result_reg[28]_i_1/CI
CARRY4 (Prop_carry4_CI_O[0])
0.232 15.986 r accumulated_result_reg[28]_i_1/O[0]
net (fo=1, unplaced) 0.000 15.986 accumulated_result_reg[28]_i_1_n_7
FDCE r accumulated_result_reg[28]/D
------------------------------------------------------------------- -------------------
(clock axis_clk rise edge)
15.000 15.000 r
0.000 15.000 r axis_clk (IN)
net (fo=0) 0.000 15.000 axis_clk
r axis_clk_IBUF_inst/I
IBUF (Prop_ibuf_I_O) 0.838 15.838 r axis_clk_IBUF_inst/O
net (fo=1, unplaced) 0.760 16.598 axis_clk_IBUF
r axis_clk_IBUF_BUFG_inst/I
BUFG (Prop_bufg_I_O) 0.091 16.689 r axis_clk_IBUF_BUFG_inst/O
net (fo=278, unplaced) 0.439 17.128 axis_clk_IBUF_BUFG
FDCE r accumulated_result_reg[28]/C
clock pessimism 0.184 17.311
clock uncertainty -0.035 17.276