From 0850e9f71608d041b059e65169d22ffaabcf7607 Mon Sep 17 00:00:00 2001 From: Ankit Pashiney Date: Mon, 9 Apr 2012 17:24:06 -0700 Subject: [PATCH] ARM: tegra: dvfs: update DVFS table for Kai update DVFS table for kai. bug 945613 Signed-off-by: Ankit Pashiney Change-Id: If4d2e814bc01df1d14ae05b8f5c557d387ae19e4 Reviewed-on: http://git-master/r/95463 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Ankit Pashiney Tested-by: Ankit Pashiney Reviewed-by: Yu-Huan Hsu --- arch/arm/mach-tegra/board-kai-memory.c | 148 +++---------------------- 1 file changed, 14 insertions(+), 134 deletions(-) diff --git a/arch/arm/mach-tegra/board-kai-memory.c b/arch/arm/mach-tegra/board-kai-memory.c index 5a22cebcfff..1f812ece741 100644 --- a/arch/arm/mach-tegra/board-kai-memory.c +++ b/arch/arm/mach-tegra/board-kai-memory.c @@ -26,126 +26,6 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { - { - 0x32, /* Rev 3.2 */ - 12750, /* SDRAM frequency */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000002, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000005, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_QUSE */ - 0x00000004, /* EMC_QRST */ - 0x00000009, /* EMC_QSAFE */ - 0x0000000b, /* EMC_RDV */ - 0x00000060, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000005, /* EMC_TXSR */ - 0x00000005, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000064, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000000, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00004288, /* EMC_FBIO_CFG5 */ - 0x007800a4, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x000fc000, /* EMC_DLL_XFORM_DQS0 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS1 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS2 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS3 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS4 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS5 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS6 */ - 0x000fc000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ0 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ1 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ2 */ - 0x000fc000, /* EMC_DLL_XFORM_DQ3 */ - 0x000002a0, /* EMC_XM2CMDPADCTRL */ - 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77fff884, /* EMC_XM2CLKPADCTRL */ - 0x01f1f108, /* EMC_XM2COMPPADCTRL */ - 0x05057404, /* EMC_XM2VTTGENPADCTRL */ - 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ - 0x08000168, /* EMC_XM2QUSEPADCTRL */ - 0x08000000, /* EMC_XM2DQSPADCTRL3 */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000040, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */ - 0x00050001, /* MC_EMEM_ARB_CFG */ - 0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0502, /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - 0xe8000000, /* EMC_FBIO_SPARE */ - 0xff00ff00, /* EMC_CFG_RSV */ - }, - 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x00000001, /* EMC_CFG.PERIODIC_QRST */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000001, /* EMC_CFG.DYN_SELF_REF */ - }, { 0x32, /* Rev 3.2 */ 25500, /* SDRAM frequency */ @@ -526,7 +406,7 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000005, /* EMC_WDV */ 0x00000005, /* EMC_QUSE */ 0x00000004, /* EMC_QRST */ - 0x00000009, /* EMC_QSAFE */ + 0x0000000a, /* EMC_QSAFE */ 0x0000000b, /* EMC_RDV */ 0x00000607, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ @@ -666,20 +546,20 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000005, /* EMC_TCLKSTOP */ 0x00000a2a, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ - 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00007088, /* EMC_FBIO_CFG5 */ 0x002600a4, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00014000, /* EMC_DLL_XFORM_DQS0 */ - 0x00014000, /* EMC_DLL_XFORM_DQS1 */ - 0x00014000, /* EMC_DLL_XFORM_DQS2 */ - 0x00014000, /* EMC_DLL_XFORM_DQS3 */ - 0x00014000, /* EMC_DLL_XFORM_DQS4 */ - 0x00014000, /* EMC_DLL_XFORM_DQS5 */ - 0x00014000, /* EMC_DLL_XFORM_DQS6 */ - 0x00014000, /* EMC_DLL_XFORM_DQS7 */ + 0x00034000, /* EMC_DLL_XFORM_DQS0 */ + 0x00034000, /* EMC_DLL_XFORM_DQS1 */ + 0x00034000, /* EMC_DLL_XFORM_DQS2 */ + 0x00034000, /* EMC_DLL_XFORM_DQS3 */ + 0x00034000, /* EMC_DLL_XFORM_DQS4 */ + 0x00034000, /* EMC_DLL_XFORM_DQS5 */ + 0x00034000, /* EMC_DLL_XFORM_DQS6 */ + 0x00034000, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ @@ -696,10 +576,10 @@ static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = { 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00020000, /* EMC_DLL_XFORM_DQ0 */ - 0x00020000, /* EMC_DLL_XFORM_DQ1 */ - 0x00020000, /* EMC_DLL_XFORM_DQ2 */ - 0x00020000, /* EMC_DLL_XFORM_DQ3 */ + 0x00034000, /* EMC_DLL_XFORM_DQ0 */ + 0x00034000, /* EMC_DLL_XFORM_DQ1 */ + 0x00034000, /* EMC_DLL_XFORM_DQ2 */ + 0x00034000, /* EMC_DLL_XFORM_DQ3 */ 0x000002a0, /* EMC_XM2CMDPADCTRL */ 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */