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;
; IDENTIFICATION
; --------------
;
; PRODUCT CODE: AC-8186C-MC
; PRODUCT NAME: CVKAAC0 CSI-11 BSC INST
; PRODUCT DATE: 01-NOVEMBER-1978
; MAINTAINER: DIAGNOSTIC ENGINEERING
; AUTHOR: PERVEZ A. ZAKI
; MODIFIED BY: BARRY SUSSMAN 01-NOV-77 A
; BARRY SUSSMAN 01-NOV-77 A
;
; The information in this document is subject to change without
; notice and should not be construed as a commitment by Digital
; Equipment Corporation. Digital Equipment Corporation assumes no
; responsibility for any error that may appear in this document.
;
; No responsibility is assumed for the use or reliability of
; software on equipment that is not supplied by Digital or its
; affiliated companies.
;
; Copyright (c) 1975, 1978 by Digital Equipment Corporation
;
; The following are trademarks of Digital Equipment Corporation:
;
; DIGITAL PDP UNIBUS MASSBUS
; DEC DECUS DECTAPE
;_____________________________________________________________________________
;
; CONTENTS
; --------
; 1. Abstract
; 2. Requirements
; 2.1 Equipment
; 2.2 Storage
; 2.3 Preliminary programs
; 3. Loading procedure
; 4. Starting procedure
; 4.1 Starting address
; 4.2 Program and/or operator action
; 5. Operating procedure
; 6. Errors
; 6.1 Error reporting
; 6.2 Error recovery
; 7. Restrictions
; 8. Miscellaneous
; 8.1 Execution time
; 8.2 Stack pointer
; 8.3 Pass counter
; 8.4 Test number
; 8.5 Power fail
; 9. Program description
;_____________________________________________________________________________
;
; 1. Abstract
;
; This program tests the LSI-11 basic instruction set
; in all modes. The diagnostic is designed to run under
; both APT and ACT systems
;
; 2. Requirements
; 2.1 Equipment
;
; LSI-11 standard computer and 4K of memory
;
; 2.2 Storage
;
; Program storage - the routines use memory 0-17500
;
; 2.3 Preliminary programs
;
; None
;
; 3. Loading procedure
;
; Use standard procedure for abs tapes.
;
; 4. Starting procedure
; 4.1 Starting address
;
; After loading the program it should always be started at 200.
; if it is desired to save the pass counter then clear the
; location $TESTN (i.e. location 102) and restart from 450 otherwise
; the program can be restarted at 200. If it is desired to go to a test
; other than test #0 then place the test number in location $TESTN
; and restart the program at 450, in which case the program will halt
; at location 464 and will wait for the operator to place the
; starting address of the desired test in PC (R7) and type a P.
;
; 4.2 Program and/or operator action
;
; 1) Place LTC switch in off position.
; 2) Load program into memory using abs loader.
; 3) Type 200G (there are no switch settings and this diagnostic
; does not use software switch location $SWREG)
; 4) The program will loop and "END PASS" will be typed after
; the first pass and then every 377 passes. However type out
; will be suppressed if bit 5 of location $ENVM is high
; 5) A minimum of two passes should always be run.
;
; 5. Operating procedure
; 5.1 Operating mode
;
; An 8-bit byte $ENVM (i.e. location 117) has been used to define
; the operating mode. All typeouts can be suppressed by making
; bit 5 of byte $ENVM high. In other words by placing a 20000 in
; location 116.
;
; 5.2 Trap catcher
;
; A ".+2" - "HALT" sequence is repeated from 0-776 to catch
; any unexpected traps. Thus any unexpected traps or interrupts
; will halt at the vector +2.
;
; 6. Errors
; 6.1 Error reporting
;
; On finding an error the processor will come to a halt after
; placing the error number in location $FATAL (i.e. location 100).
; In most cases the comments besides the halts tell what was being
; checked. In some cases the test can get to a halt via 2 ways:
;
; 1) wrong test sequence
; 2) error in actual test
;
; When a halt does occur it is recommended that the test sequence
; location (i.e. location 102) be checked to verify that it matches
; the present test number. If it doesn't, then the halt occurred
; because the test sequence was not correct otherwise the halt is
; due to an error in the test.
;
; 6.2 Error recovery
;
; Restart at 200 or 450 (see sec 4.1)
;
; 7. Restrictions
;
; None
;
; 8. Miscellaneous
; 8.1 Execution time
;
; Execution time of the diagnostic is less than a second, first
; "END PASS" will be typed out within a second and every consecutive
; "END PASS" will be typed out within 20 seconds (see sec 4.2)
;
; When running under apt in a script, the first pass run time
; and subsequent pass run times are one (1) second.
;
; 8.2 Stack pointer
;
; Stack is initially set to 450
;
; 8.3 Pass count
;
; A 16-bit location "$PASS" (i.e. location 104) is used to keep
; pass count. It can be cleared by restarting the program at 200
;
; 8.4 Test number
;
; A 16-bit location "$TESTN" (i.e. location 102) is used to keep track
; of the test number, upper byte of this location gives the iteration
; number and the lower byte the test that was being executed
;
; 8.5 Power fail
;
; The diagnostic can be power failed with no errors. To use,
; start the diagnostic as usual and power down then up at any time.
; The program should type "POWER" and restart at 450 with test #0.
; However the diagnostic will not recover if it is stored in a
; memory not capable of holding data with power down
;
; 9. Program description
;
; This program tests all the basic instructions of the LSI-11 (except
; trap-type) which includes control chip, data chip, micROMs, PLA
; and other circuitry on the LSI-11 CPU module. Trap diagnostic
; should also be run make sure that the basic LSI-11 is functional.
; This diagnostic does not make a pass with T-bit set.
;_____________________________________________________________________________
;
HOEP = 0 ; halt on end-of-pass
;_____________________________________________________________________________
;
; LSI-11 macro instruction exerciser
;
.asect
.nlist mc, md, cnd
.list me
.title CVKAAC
;_____________________________________________________________________________
;
; Copyright (c) 1975, 1978 Digital Equipment Corp.
; Maynard, Mass. 01754
;
; Program by Pervez Zaki
;
; This program was assembled using the PDP-11 maindec sysmac
; package (maindec-11-dzqac-c3), Jan 19, 1977.
;
$tn = 1 ;
$swr = 160000 ; halt on error,
. = 0 ; loop on test
; inhibit error typeout
;_____________________________________________________________________________
;
; Trap catchers of .+2 and halt in locations 0 thru 776 (it is nlisted)
; Hooks required by act11
;
; $svpc = . ; save PC
; . = 46 ; set loc 46 to address
; $endad ; of $endad in $eop
; . = 52 ;
; .word 0 ;
; . = $svpc ; restore PC
; ;
R0 = %0 ;
R1 = %1 ;
R2 = %2 ;
R3 = %3 ;
R4 = %4 ;
R5 = %5 ;
SP = %6 ;
PC = %7 ;
;
clnz = 254 ;
errnm = 1 ;
nops = 260 ;
sevc = 263 ;
senvc = 273 ;
$tn = 0 ;
.type = iot ;
;_____________________________________________________________________________
;
.macro jmpR0 ; MACRO-11 generates an error Z
.word 000120 ; jmp (R0)+ works differently
.endm ; on PDP-11 models
;
.macro jsrR0 ;
.word 004720 ; jsr PC, (R0)+
.endm ;
;
.macro movR0p ;
.word 010020 ; mov R0, (R0)+
.endm ;
;
.macro movR0m ;
.word 010040 ; mov R0, -(R0)
.endm ;
;
.macro addR0 ;
.word 060020 ; add R0, (R0)+
.endm ;
;_____________________________________________________________________________
;
.macro vect, offset, adr, val ;
. = offset ;
.if nb, <adr> ;
.word adr ;
.iff ;
.word .+2 ;
.endc ;
.if nb, <val> ;
.word val ;
.iff ;
.word 0 ;
.endc ;
.endm ;
;_____________________________________________________________________________
;
.nlist
vect 0 ;
vect 4 ;
vect 10 ;
vect 14 ;
vect 20, type ; type out the message
vect 24, 200 ; power fail entry
vect 30 ;
vect 34 ;
vect 40 ;
vect 44, $apthd, $endad ;
vect 50 ;
vect 54 ;
vect 60 ;
vect 64 ;
vect 70 ;
.list ;
;_____________________________________________________________________________
;
; APT mailbox-etable
;
. = 74 ;
.word 76 ; overlapping with vector
.even ;
$mail: ; ; apt mailbox
$msgty: .word 0 ; amsgty ; message type code
$fatal: .word 0 ; afatal ; fatal error number
$testn: .word 0 ; atestn ; test number
$pass: .word 0 ; apass ; pass count
$devct: .word 0 ; adevct ; device count
$unit: .word 0 ; aunit ; I/O unit number
$msgad: .word 0 ; amsgad ; message address
$msglg: .word 0 ; amsglg ; message length
$etable: ; ; apt environment table
$env: .byte 0 ; aenv ; environment byte
$envm: .byte 0 ; aenvm ; environment mode bits
$swreg: .word 0 ; aswreg ; apt switch register
$uswr: .word 0 ; auswr ; user switches
$cpuop: .word 0 ; acpuop ; cpu type, options
; bits 15-11=cpu type
; 11/04=01, 11/05=02
; 11/20=03, 11/40=04
; 11/45=05, 11/70=06
; PDQ=07, Q=10
; bit 10 - real time clock
; bit 9 - floating point
$etend: ; bit 8 - memory management
;_____________________________________________________________________________
;
; APT parameter block
; Set locations 24 and 44 as required for apt (set above by vect macro)
;
; .$x = . ; save current location
; . = 24 ; set power fail to start
; 200 ; of program for apt start up
; . = 44 ; point to apt indirect address
; $apthd ; point to apt header block
; . = .$x ; reset location counter
;
; Setup apt parameter block as defined in the apt-pdp11 diagnostic
; interface spec.
;
$apthd:
$hibts: .word 0 ; two high bits of 18 bit mailbox
$mbadr: .word $mail ; address of apt mailbox (0-15)
$tstm: .word 1 ; run time of longest test
$pastm: .word 1 ; run time in secs of 1st pass
$unitm: .word 0 ; additional run time (secs)
; of a pass for each add unit
.word $etend-$mail/2 ; length of mailbox-etable
;
. = $apthd ;
adr: ;
. = adr + 2 ;
adr1: ;
. = adr1 + 2 ;
adr2: ;
. = adr2 + 2 ;
dummy: ;
. = dummy + 2 ;
temp: ;
. = temp + 2 ;
temp1: ;
. = temp1 + 2 ;
temp2: ;
. = temp2 + 2 ;
;
tps: .word 177564 ; output TTY status
tpb: .word 177566 ; output TTY buffer
;
mark2: mark 2 ;
endpas: .asciz <15><12>" END PASS" ;
.even ;
power: .asciz <15><12>/POWER/ ;
.even ;
.blkw 19. ;
; . = 20 ;
; type ; type routine
; 0 ; generated by vect
;_____________________________________________________________________________
;
; Starting of the program
;
. = 200 ;
mov #pwrdn, @#24 ; service power down routine
mov #$etable, R0 ; on any future power down
2$: clr -(R0) ; start cleaning the stack
cmp R0, #$mail ; for initialization
bhi 2$ ;
jmp start ;
;
vect 230 ;
vect 234 ;
vect 240 ;
vect 244 ;
vect 250 ;
vect 254 ;
vect 260 ;
vect 264 ;
vect 270 ;
vect 274 ;
vect 300 ;
vect 304 ;
vect 310 ;
vect 314 ;
vect 320 ;
vect 324 ;
vect 330 ;
vect 334 ;
vect 340 ;
vect 344 ;
vect 350 ;
vect 354 ;
vect 360 ;
vect 364 ;
vect 370 ;
vect 374 ;
vect 400 ;
vect 404 ;
vect 410 ;
vect 414 ;
vect 420 ;
vect 424 ;
vect 430 ;
vect 434 ;
vect 440 ;
vect 444 ;
;_____________________________________________________________________________
;
. = 450 ;
start: mov #start, SP ; set the stack pointer
mov #$testn, R5 ; the address of testn in R5
tst (R5) ; check the sequence counter
beq nobit ; if this is the starting of
; the test then go to nobit test
halt ; otherwise halt and wait for
; the operator to start at the
; proper test number
;_____________________________________________________________________________
;
; TEST 0 - check branch instructions with zero condition codes
;
nobit: cmp (R5), #0 ; if in wrong sequence go to
bne cc0 ; halt at end of the test
1$: inc (R5) ;
ccc ; zero condition codes
bcs cc0 ; NZVC = 0000
bvs cc0 ;
beq cc0 ;
bmi cc0 ;
nops ; check nops instruction
bcs cc0 ; (opcode 260)
bvs cc0 ;
beq cc0 ;
bmi cc0 ;
blt cc0 ;
ble cc0 ;
blos cc0 ;
bhi endcc0 ;
;
cc0: mov #1, -(R5) ; one of the above branches
inc -(R5) ; failed or wrong sequence
halt ;
endcc0: bvc nbit ;
;_____________________________________________________________________________
;
; TEST 1 - check branch instructions with N-bit set
;
nbit: cmp (R5), #1 ; if in wrong sequence go to
bne cc1 ; halt at end of the test
1$: inc (R5) ;
sen ; N-bit is set, NZVC = 1000
bpl cc1 ;
beq cc1 ;
bge cc1 ;
bgt cc1 ;
bcs cc1 ;
blos cc1 ;
blo cc1 ;
ble endcc1 ;
;
cc1: mov #2, -(R5) ; one of the above branches
inc -(R5) ; failed or wrong sequence
halt ;
endcc1: bne vbit ;
;_____________________________________________________________________________
;
; TEST 2 - check branch instructions with N&V bits set
;
vbit: cmp (R5), #2 ;
bne cc2 ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
sen ;
sev ; V and N bit set, NZVC = 1010
bvc cc2 ;
beq cc2 ;
bpl cc2 ;
bcs cc2 ;
blt cc2 ;
ble cc2 ;
blos cc2 ;
blo cc2 ;
bgt endcc2 ;
;
cc2: mov #3, -(R5) ; one of the above branches
inc -(R5) ; failed or wrong sequence
halt ;
endcc2: bge cbit ;
;_____________________________________________________________________________
;
; TEST 3 - check branch instructions with N, V&C bits set
;
cbit: cmp (R5), #3 ;
bne cc3 ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
sen ;
sev ; C, V and N bits are set
sec ; NZVC = 1011
beq cc3 ;
bpl cc3 ;
bvc cc3 ;
blt cc3 ;
ble cc3 ;
bhi cc3 ;
bge zbit ;
;
cc3: mov #4, -(R5) ; one of the above branches
inc -(R5) ; failed or wrong sequence
halt ;
;_____________________________________________________________________________
;
; TEST 4 - check branch instructions with N, Z, V&C bits set
;
zbit: cmp (R5), #4 ;
bne cc4 ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
sen ;
sev ;
sec ;
sez ; all bits set, NZVC = 1111
bne cc4 ;
bpl cc4 ;
bvc cc4 ;
bcc cc4 ;
blt cc4 ;
bgt cc4 ;
bhi cc4 ;
beq yescc ;
;
cc4: mov #5, -(R5) ; one of the above branches
inc -(R5) ; failed or wrong sequence
halt ;
;_____________________________________________________________________________
;
; TEST 5 - check branch instructions with all the condition codes set
;
yescc: cmp (R5), #5 ;
bne cc6 ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
scc ; NZVC = 1111
bpl cc6 ;
bne cc6 ;
bvc cc6 ;
bcc cc6 ;
nop ; check nop instruction
bpl cc6 ;
bne cc6 ;
bvc cc6 ;
bcc cc6 ;
blos notcc ;
;
cc6: mov #6, -(R5) ; one of the above branches
inc -(R5) ; failed or wrong sequence
halt ;
;_____________________________________________________________________________
;
; TEST 6 - clear the condition codes
;
notcc: cmp (R5), #6 ;
bne cc5 ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
scc ; NZVC = 1111
clc ; NZVC = 1110
bcs cc5 ;
clv ; NZVC = 1100
bvs cc5 ;
clz ; NZVC = 1000
beq cc5 ;
cln ; NZVC = 0000
bmi cc5 ;
bhi endcc5 ;
cc5: mov #7, -(R5) ; one of the above branches
inc -(R5) ; failed or wrong sequence
halt ;
endcc5: bpl branch ;
;_____________________________________________________________________________
;
; TEST 7 - check upward and backward branches
;
branch: cmp (R5), #7 ;
beq 1$ ; if in wrong sequence
mov #10, -(R5) ; go to halt
inc -(R5) ;
halt ;
1$: inc (R5) ;
br 4$ ; check branch forward
mov #11, -(R5) ; and backward
inc -(R5) ; forward branch failed
halt ;
2$: br 3$ ;
mov #12, -(R5) ;
inc -(R5) ; forward branch failed
halt ;
3$: br 5$ ;
mov #13, -(R5) ;
inc -(R5) ;
halt ; forward branch failed
4$: br 2$ ;
mov #14, -(R5) ;
inc -(R5) ;
halt ; backward branch failed
5$: br jmp1 ;
;_____________________________________________________________________________
;
; TEST 10 - check jmp instructions for mode 1
;
jmp1: cmp (R5), #10 ;
bne endjp1 ; if in wrong sequence go to
1$: inc (R5) ; halt at the end of the test
mov #2$, R0 ; test jump instruction mode 1
scc ;
jmp (R0) ;
mov #15, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
2$: bpl 3$ ;
bne 3$ ;
bvc 3$ ;
bcs 4$ ;
3$: mov #16, -(R5) ;
inc -(R5) ;
halt ; wrong cc
;
4$: cmp R0, #2$ ;
beq 5$ ; continue if R0 is OK
mov #17, -(R5) ;
inc -(R5) ;
halt ;
;
5$: mov #jmp2, R0 ; test jump instruction mode 1
jmp (R0) ;
;
endjp1: mov #20, -(R5) ;
inc -(R5) ; jump instruction failed
halt ; or wrong sequence
;_____________________________________________________________________________
;
; TEST 11 - check jmp instructions for modes 2 and 3
;
jmp2: cmp (R5), #11 ;
bne endjp3 ; if in wrong sequence go to
inc (R5) ; halt at the end of test
mov #3$, R0 ; test jump instruction mode 2
scc ;
jmpR0 ; jmp (R0)+
mov #21, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
3$: bpl 4$ ;
bne 4$ ;
bvc 4$ ;
bcs 5$ ;
4$: mov #22, -(R5) ;
inc -(R5) ;
halt ; wrong cc
;
5$: cmp R0, #3$+2 ; is there auto inc?
beq 6$ ;
mov #23, -(R5) ;
inc -(R5) ;
halt ; mode 2 failed for jmp instruction
;
6$: mov #jmp3, R0 ; test jump instruction mode 2
jmpR0 ; jmp (R0)+
mov #24, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
jmp3: mov #3$, temp ; test jump instruction mode 3
mov #4$, temp+2 ;
mov #temp, R0 ;
scc ;
jmp @(R0)+ ;
mov #25, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
3$: cmp @(R0), 4$ ; is there auto inc?
beq 4$ ;
mov #26, -(R5) ;
inc -(R5) ;
halt ; jmp instruction failed in mode 2
;
4$: mov #jmp4, temp ; test jump instruction mode 3
mov #temp, R0 ;
jmp @(R0)+ ;
endjp3: mov #27, -(R5) ;
inc -(R5) ;
halt ; lmp error or wrong sequence
;_____________________________________________________________________________
;
; TEST 12 - test jump instruction for mode 4, 5
;
jmp4: cmp (R5), #12 ;
bne endjp5 ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
mov #3$, R0 ; test jump instruction mode 4
scc ;
jmp -(R0) ;
mov #30, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
br 4$ ; jump should land here
;
3$: mov #31, -(R5) ;
inc -(R5) ;
halt ; no auto decrement from jmp4
;
4$: cmp #3$-2, R0 ; check R0
beq 5$ ;
mov #32,-(R5) ;
inc -(R5) ;
halt ;
;
5$: mov #jmp5+2, R0 ; test jump instruction mode 4
jmp -(R0) ;
mov #33, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
jmp5: mov #3$, temp1 ; test jump instruction mode 5
mov #temp1, R0 ;
mov #4$,temp1-2 ;
jmp @-(R0) ;
mov #34, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
3$: mov #35, -(R5) ;
inc -(R5) ;
halt ; error, no auto decrement
;
4$: cmp #temp1-2, R0 ; check R0
beq 5$ ;
mov #36, -(R5) ;
inc -(R5) ; jump instruction
halt ; failed in mode 5
5$: mov #3$, temp1 ; test jump instruction mode 5
mov #temp1, R0 ;
mov #jmp6, temp1-2 ;
jmp @-(R0) ;
;
endjp5: mov #37, -(R5) ;
inc -(R5) ;
halt ; jump error or wrong sequence
;_____________________________________________________________________________
;
; TEST 13 - test jmp instruction for mode 6 and 7
;
jmp6: cmp (R5), #13 ;
bne endjp7 ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
mov #1$+6, R3 ;
jmp -6(R3) ;
mov #40, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
1$: cmp R3, #1$+6 ; check R3
beq 2$ ;
mov #41, -(R5) ; wrong value in register after
inc -(R5) ; jump mode 6 or jump instruction
halt ; failed in mode 6
;
2$: jmp 3$-.-4(PC) ; test jump instruction mode 6
mov #42, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
3$: mov #jmp7, R3 ; jump should land here
jmp 0(R3) ;
mov #43, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
jmp7: mov #temp, R3 ;
mov #1$, (R3) ;
jmp @(R3) ;
mov #44, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
1$: mov #3$, (R3) ; test jump instruction mode 7
mov #temp-4, R0 ;
jmp @4(R0) ;
mov #45, -(R5) ;
inc -(R5) ;
halt ; jump instruction failed
;
3$: mov #jsrtst, temp ; continue
mov #temp, R0 ;
jmp @0(R0) ;
;
endjp7: mov #46, -(R5) ;
inc -(R5) ;
halt ; jump error or sequence error
;_____________________________________________________________________________
;
; TEST 14 - check jsr and mark instructions
;
jsrtst: cmp (R5), #14 ;
bne endjsr ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
mov #start, SP ; set up stack pointer
scc ;
jsr PC, 3$ ;
1$: mov #47, -(R5) ;
inc -(R5) ;
halt ; jsr instruction failed
;
2$: cmp #start, SP ; has SP been restored?
beq jsrm ;
mov #50, -(R5) ;
inc -(R5) ; SP was not restored by
halt ; rts instruction
;
3$: bpl 4$ ;
bne 4$ ;
bvc 4$ ;
bcs 5$ ;
4$: mov #51, -(R5) ;
inc -(R5) ;
halt ; wrong cc
;
5$: cmp #start-2, SP ; was the SP effected?
beq 6$ ;
mov #52, -(R5) ;
inc -(R5) ; wrong SP after execution
halt ; of jsr instruction
;
6$: cmp #1$, (SP) ; is the return address 1$?
beq 7$ ;
mov #53, -(R5) ;
inc -(R5) ; SP did not have correct
halt ; return address after
; execution of jsr instruction
7$: mov #2$, (SP) ; set 2$ as the return address
RTS PC ;
mov #54, -(R5) ;
inc -(R5) ;
halt ; rts instruction failed
;
jsrm: mov R5,-(SP) ; mov R5 to stack
mov dummy, -(SP) ;
mov dummy, -(SP) ;
mov mark2, -(SP) ; store mark 2 on the stack
mov R5, R3 ; save R5 in R3
jsr R4, 10$ ;
;
1$: mov #55, -(R5) ;
inc -(R5) ;
halt ; jsr instruction failed
;
2$: bpl 3$ ;
bne 3$ ;
bvc 3$ ;
bcs 4$ ;
3$: mov #56, -(R3) ;
inc -(R3) ;
halt ; wrong cc
;
4$: cmp #$testn, R5 ;
beq 5$ ;
mov #57, -(R3) ;
inc -(R3) ;
halt ; mark instruction failed
;
5$: cmp #start, SP ;
beq 6$ ;
mov #60, -(R5) ;
inc -(R5) ;
halt ; mark instruction failed
;
6$: mov #12$, R1 ; place the address of 12$
jsr R0, (R1) ; in R1 go to tag 12$
7$: mov #61, -(R5) ;
inc -(R5) ;
halt ; jsr instruction failed
mov #62, -(R5) ;
inc -(R5) ; rts brought the program
halt ; back in wrong place
;
8$: cmp #start, SP ;
beq regs ;
mov #63, -(R5) ;
inc -(R5) ;
halt ; stack pointer was not reset
;
10$: cmp R4, #1$ ; is the return address = 1$ ?
beq 11$ ;
mov #64, -(R5) ;
inc -(R5) ; wrong return address
halt ; in linkage register R4
;
11$: mov SP, R5 ; set up address in R5
tst (R5)+ ; at mark 2 instruction
mov #2$, (SP) ; set return address
scc ;
rts R5 ; return using R5 and in-turn
mov #65, -(R5) ; using mark instruction
inc -(R5) ;
halt ; rts instruction failed
;
12$: cmp R0, #7$ ; does R0 contain
beq 13$ ; the return address ?
mov #66, -(R5) ;
inc -(R5) ; wrong return address in
halt ; linkage register R0
;
13$: mov #8$, R0 ; set return address at 8$
rts R0 ;
;
endjsr: mov #67, -(R5) ;
inc -(R5) ; rts instruction failed
halt ; or sequence error
;_____________________________________________________________________________
;
; TEST 15 - check register selection
;
regs: cmp (R5), #15 ;
bne eregs ; if in wrong sequence go to
inc (R5) ; halt at the end of the test
mov SP, temp ; save the stack pointer
mov #1, R0 ; load the registers
mov #4, R1 ;
mov #20, R2 ;
mov #100, R3 ;
mov #400, R4 ;
clr SP ;
add R0, SP ; add up the registers
add R1, SP ;
add R2, SP ;
add R3, SP ;
add R4, SP ;
add R5, SP ;
cmp #$testn+525, SP ; check it
bne 1$ ; failed
mov temp, SP ; restore stack pointer
br tstb0 ; continue
1$: mov temp, SP ; restore stack pointer
eregs: mov #70, -(R5) ;
inc -(R5) ; register selection failure
halt ; or sequence error
;
; check byte instructions, destination mode 0 only
;_____________________________________________________________________________
;
; TEST 16 - new instructions used in this section are tstb, clrb, movb
;
tstb0: cmp (R5), #16 ;
beq 2$ ; if in wrong sequence
mov #71, -(R5) ; go to halt below
inc -(R5) ;
halt ; program is in wrong sequence
;
2$: inc (R5) ;
scc ;
clrb R0 ; clear the register
jsr PC, @#$cc4 ; check for cc = 4
tstb R0 ; check it
jsr PC, @#$cc4 ; check for cc = 4
movb #377, R1 ; load the register
jsr PC, @#$cc10 ; check for cc = 10
tstb R1 ; check it
jsr PC, @#$cc10 ; check for cc = 10
;_____________________________________________________________________________
;
; TEST 17 - new instructions used in this section are cmpb, bisb
;
cmpb0: cmp (R5), #17 ;
bne ecmpb0 ; if in wrong sequence go to
1$: inc (R5) ; halt at the end of the test
scc ;
bisb #377, R2 ; load register
jsr PC, @#$cc11 ; check for cc = 11
cmpb #377, R2 ; check compare
beq 2$ ; continue if OK
mov #72, -(R5) ;
inc -(R5) ; bisb or cmpb
halt ; instruction failed
;
2$: movb #77, R0 ;
cmpb R0, R2 ; check it again
bpl 3$ ; continue if OK
mov #73, -(R5) ;
inc -(R5) ; cmpb instruction failed
halt ; (wrong cc)
;