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Micro Assembler

The Micro Assembler to compile the microcode was develeoped in Python. It compiles the multiple source files in two passes and writes out the united object file in Verlig Memory format and optionally the TTL/PLA translation fields content. Program uses standard Python 3.x libraries only and has no external dependencies.

Usage

cp16mic.py srcfile [srcfile ..] [-l|--lst lstfile] [-o|--obj objfile] [-t|--ttl ttlfile]

Numeric, literals values and labels

  • axxxx - identifier should start with letter
  • . (point) - current location counter, assignable
  • nnnn$ - is treated as local label
  • 0xNNNN - always hexadecimal
  • 0bNNNN - always binary
  • NNNN. - always decimal
  • 0NNNN - always octal
  • NNNN - depends on .radix settings
  • 'N' - character code
  • "string" - string literal (supports \,",')

Supported directives

The following directives are supported:

  • name=expr - assign the name with specified expression, ")(~+-*/|&^" operations supported, C-language priorities
  • .title "string" - provide the title "string", ignored
  • .radix expr - provide default base for the numeric values, 8 is assigned at the beginning of each source file by default, 8 an 10 values are supported.
  • .align expr - align the location counter on specified power of 2
  • .tran name, expr - defines name of translation with specified value
  • .reg name, expr - defines name of register with specified value
  • .org expr - assign the specified value to location counter
  • .loc expr - assign the specified value to location counter
  • .end - finished the current source file processing

Predefined register names

These names are predefined as register names:

  • G, GL, GH - access by G index register
  • RBA, RBAL, RBAH - bus address register, lower and upper halves
  • RSRC, RSRCL, RSRCH - source register, lower and upper halves
  • RDST, RDSTL, RDSTH - destination register, lower and upper halves
  • RIR, RIRL, RIRH - PDP-11 instruction register, lower and upper halves
  • RPSW, RPSWL, RPSWH - PDP-11 status word register, lower and upper halves
  • SP, SPL, SPH - PDP-11 stack pointer register, lower and upper halves
  • PC, PCL, PCH - PDP-11 program counter register, lower and upper halves

These names are predefined as flag bitmasks:

  • I4, I5, I6 - interrupt set/clear masks
  • C, V, Z, N, T - PDP-11 arithmetic flags and T-bit
  • C8, C4, ZB, NB - MCP-1600 ALU flags
  • UB, LB, UBC, LBC, RMW - input/output mode
  • TG6, TG8 - instruction fetch control

These names are predefined as extension field bits:

  • LRR - load location counter from return register
  • RSVC - read next instruction

Standard MCP-1600 mnemonics, defined in vendor documentation are supported.