From c01fb18c9eb6e4a0afbc54b5eab5b5d878e5c732 Mon Sep 17 00:00:00 2001 From: BRH Date: Thu, 9 May 2024 18:51:00 +0200 Subject: [PATCH] added report --- README.md | 10 +- REPORT/CVA6_With_custom_mem-1.pdf | Bin 0 -> 687113 bytes REPORT/README.md | 19 + REPORT/fpga_exec_log.png | Bin 0 -> 69466 bytes .../cva6_fpga.check_timing.rpt | 126 + .../cva6_fpga.timing.rpt | 233 + .../cva6_fpga.timing_WORST_100.rpt | 10417 +++++++++++++++ .../cva6_fpga.utilization.rpt | 841 ++ .../reports_cva6_fpga_synth/cva6_fpga.cdc.rpt | 20 + .../cva6_fpga.check_timing.rpt | 663 + .../cva6_fpga.clock_interaction.rpt | 26 + .../cva6_fpga.timing.rpt | 237 + .../cva6_fpga.timing_WORST_100.rpt | 10617 ++++++++++++++++ .../cva6_fpga.utilization.rpt | 847 ++ REPORT/simulation_uart_log.png | Bin 0 -> 55467 bytes 15 files changed, 24053 insertions(+), 3 deletions(-) create mode 100644 REPORT/CVA6_With_custom_mem-1.pdf create mode 100644 REPORT/README.md create mode 100644 REPORT/fpga_exec_log.png create mode 100644 REPORT/reports_cva6_fpga_impl/cva6_fpga.check_timing.rpt create mode 100644 REPORT/reports_cva6_fpga_impl/cva6_fpga.timing.rpt create mode 100644 REPORT/reports_cva6_fpga_impl/cva6_fpga.timing_WORST_100.rpt create mode 100644 REPORT/reports_cva6_fpga_impl/cva6_fpga.utilization.rpt create mode 100644 REPORT/reports_cva6_fpga_synth/cva6_fpga.cdc.rpt create mode 100644 REPORT/reports_cva6_fpga_synth/cva6_fpga.check_timing.rpt create mode 100644 REPORT/reports_cva6_fpga_synth/cva6_fpga.clock_interaction.rpt create mode 100644 REPORT/reports_cva6_fpga_synth/cva6_fpga.timing.rpt create mode 100644 REPORT/reports_cva6_fpga_synth/cva6_fpga.timing_WORST_100.rpt create mode 100644 REPORT/reports_cva6_fpga_synth/cva6_fpga.utilization.rpt create mode 100644 REPORT/simulation_uart_log.png diff --git a/README.md b/README.md index fd501e5e..61f22f53 100644 --- a/README.md +++ b/README.md @@ -24,12 +24,16 @@ into a tighly coupled co-processor using SRAM. This SRAM should be as small a sp - You HAVE to specify the max kernel size in ./core/cvxif_example/cvxif_example_coprocessor.sv uder the "Nb_of_regs" parameter. Then, to take full advantage of this design based on a home-made TPU (Tensor Processing Unit), you need to tell -the compiler a few specific things using assembly +the compiler a few specific things using inline assembly : -- First : load data in CVXIF using ... and ... -- Then : Lunch ... +- First : load data in CVXIF using LBC and LBCU instructions +- Then : Lunch MAC instruction (this will read tensor operation result form CV-X-IF and clear all of its registers) - Finally : to further push performances, you can add load checks to avoid re-loading an already loaded kernel in memory +In this example, we modified the MNIST program (./sw/app/mnist/NetworkPropagate.c). + +More infos in ./REPORT (See pdf article). + ### Building the software binaries RISC-V binaries are built using GCC and bintuils. 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b/REPORT/reports_cva6_fpga_impl/cva6_fpga.check_timing.rpt new file mode 100644 index 00000000..50015870 --- /dev/null +++ b/REPORT/reports_cva6_fpga_impl/cva6_fpga.check_timing.rpt @@ -0,0 +1,126 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:29:28 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : check_timing -file reports_cva6_fpga_impl/cva6_fpga.check_timing.rpt +| Design : cva6_zybo_z7_20 +| Device : 7z020-clg400 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (480) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (32) +5. checking no_input_delay (2) +6. checking no_output_delay (1) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (3) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (480) +-------------------------- + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][0]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][1]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][2]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][3]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][4]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][5]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][6]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][0]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][1]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][2]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][3]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][4]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][5]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][6]/Q (HIGH) + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/gen_cache_wt.i_cache_subsystem/i_wt_dcache/gen_rd_ports[1].i_wt_dcache_ctrl/id_q_reg[0]/Q (HIGH) + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (32) +------------------------------------------------- + There are 32 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 2 input ports with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (1) +------------------------------- + There is 1 port with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (3) +------------------------------------ + There are 3 input ports with partial input delay specified. (HIGH) + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + diff --git a/REPORT/reports_cva6_fpga_impl/cva6_fpga.timing.rpt b/REPORT/reports_cva6_fpga_impl/cva6_fpga.timing.rpt new file mode 100644 index 00000000..1507f560 --- /dev/null +++ b/REPORT/reports_cva6_fpga_impl/cva6_fpga.timing.rpt @@ -0,0 +1,233 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:29:30 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_fpga_impl/cva6_fpga.timing.rpt +| Design : cva6_zybo_z7_20 +| Device : 7z020-clg400 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (MET) : 1.498ns (required time - arrival time) + Source: i_dmi_jtag/i_dmi_jtag_tap/td_o_reg/C + (falling edge-triggered cell FDCE clocked by tck {rise@0.000ns fall@50.000ns period=100.000ns}) + Destination: tdo + (output port clocked by tck {rise@0.000ns fall@50.000ns period=100.000ns}) + Path Group: tck + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 5.872ns (logic 4.015ns (68.378%) route 1.857ns (31.623%)) + Logic Levels: 1 (OBUF=1) + Output Delay: 5.000ns + Clock Path Skew: -7.128ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.000ns + Source Clock Delay (SCD): 7.128ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.501ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 1.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock tck fall edge) 0.000 0.000 f + H15 0.000 0.000 f tck (IN) + net (fo=0) 0.000 0.000 tck + H15 IBUF (Prop_ibuf_I_O) 1.500 1.500 f tck_IBUF_inst/O + net (fo=1, routed) 3.659 5.159 tck_IBUF + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 5.260 f tck_IBUF_BUFG_inst/O + net (fo=258, routed) 1.868 7.128 i_dmi_jtag/i_dmi_jtag_tap/tck_ni + SLICE_X113Y95 FDCE r i_dmi_jtag/i_dmi_jtag_tap/td_o_reg/C (IS_INVERTED) + ------------------------------------------------------------------- ------------------- + SLICE_X113Y95 FDCE (Prop_fdce_C_Q) 0.459 7.587 r i_dmi_jtag/i_dmi_jtag_tap/td_o_reg/Q + net (fo=1, routed) 1.857 9.445 tdo_OBUF + J15 OBUF (Prop_obuf_I_O) 3.556 13.001 r tdo_OBUF_inst/O + net (fo=0) 0.000 13.001 tdo + J15 r tdo (OUT) + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + clock pessimism 0.000 20.000 + clock uncertainty -0.501 19.499 + output delay -5.000 14.499 + ------------------------------------------------------------------- + required time 14.499 + arrival time -13.001 + ------------------------------------------------------------------- + slack 1.498 + +Slack (MET) : 15.620ns (required time - arrival time) + Source: i_dm_top/i_dm_csrs/dmcontrol_q_reg[ndmreset]/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/CLR + (recovery check against rising-edge clock clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 3.726ns (logic 0.580ns (15.567%) route 3.146ns (84.433%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: -0.255ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.539ns = ( 18.461 - 20.000 ) + Source Clock Delay (SCD): -0.831ns + Clock Pessimism Removal (CPR): 0.453ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.861 -0.831 i_dm_top/i_dm_csrs/clk_out1 + SLICE_X109Y24 FDCE r i_dm_top/i_dm_csrs/dmcontrol_q_reg[ndmreset]/C + ------------------------------------------------------------------- ------------------- + SLICE_X109Y24 FDCE (Prop_fdce_C_Q) 0.456 -0.375 f i_dm_top/i_dm_csrs/dmcontrol_q_reg[ndmreset]/Q + net (fo=3, routed) 1.345 0.970 i_dm_top/i_dm_csrs/ndmreset + SLICE_X109Y36 LUT2 (Prop_lut2_I0_O) 0.124 1.094 f i_dm_top/i_dm_csrs/synch_regs_q[3]_i_1/O + net (fo=4, routed) 1.801 2.895 i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]_1 + SLICE_X90Y50 FDCE f i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.606 18.461 i_rstgen_main/i_rstgen_bypass/clk_out1 + SLICE_X90Y50 FDCE r i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C + clock pessimism 0.453 18.913 + clock uncertainty -0.079 18.834 + SLICE_X90Y50 FDCE (Recov_fdce_C_CLR) -0.319 18.515 i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3] + ------------------------------------------------------------------- + required time 18.515 + arrival time -2.895 + ------------------------------------------------------------------- + slack 15.620 + + + + diff --git a/REPORT/reports_cva6_fpga_impl/cva6_fpga.timing_WORST_100.rpt b/REPORT/reports_cva6_fpga_impl/cva6_fpga.timing_WORST_100.rpt new file mode 100644 index 00000000..ab018a00 --- /dev/null +++ b/REPORT/reports_cva6_fpga_impl/cva6_fpga.timing_WORST_100.rpt @@ -0,0 +1,10417 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:29:30 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_fpga_impl/cva6_fpga.timing_WORST_100.rpt +| Design : cva6_zybo_z7_20 +| Device : 7z020-clg400 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Routed +----------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 f i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 f i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + +Slack (VIOLATED) : -0.284ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.877ns (logic 3.519ns (17.704%) route 16.358ns (82.296%)) + Logic Levels: 22 (LUT3=1 LUT4=1 LUT5=3 LUT6=17) + Clock Path Skew: -0.123ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.687ns = ( 18.313 - 20.000 ) + Source Clock Delay (SCD): -0.997ns + Clock Pessimism Removal (CPR): 0.567ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.285 2.760 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.759 -4.999 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.206 -2.793 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 -2.692 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.695 -0.997 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X56Y77 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + SLICE_X56Y77 FDCE (Prop_fdce_C_Q) 0.419 -0.578 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, routed) 1.160 0.582 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + SLICE_X56Y77 LUT6 (Prop_lut6_I0_O) 0.296 0.878 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/i___2_i_5/O + net (fo=39, routed) 0.942 1.820 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[valid] + SLICE_X53Y76 LUT3 (Prop_lut3_I1_O) 0.124 1.944 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13/O + net (fo=12, routed) 1.033 2.977 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_13_n_1 + SLICE_X53Y78 LUT6 (Prop_lut6_I1_O) 0.124 3.101 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_29/O + net (fo=4, routed) 0.961 4.061 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_op_commit_csr[2] + SLICE_X51Y77 LUT6 (Prop_lut6_I2_O) 0.124 4.185 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dcsr_q[step]_i_15/O + net (fo=2, routed) 0.781 4.967 i_ariane/i_cva6/csr_regfile_i/privilege_violation1 + SLICE_X49Y77 LUT6 (Prop_lut6_I3_O) 0.124 5.091 r i_ariane/i_cva6/csr_regfile_i/scause_q[1]_i_4/O + net (fo=12, routed) 0.695 5.785 i_ariane/i_cva6/ex_stage_i/csr_buffer_i/privilege_violation18_out + SLICE_X49Y78 LUT6 (Prop_lut6_I4_O) 0.124 5.909 r i_ariane/i_cva6/ex_stage_i/csr_buffer_i/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_16/O + net (fo=5, routed) 0.331 6.241 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_exception_csr_commit[valid] + SLICE_X49Y77 LUT4 (Prop_lut4_I1_O) 0.124 6.365 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_10/O + net (fo=180, routed) 0.759 7.124 i_ariane/i_cva6/issue_stage_i/i_scoreboard/wfi_q_reg_0 + SLICE_X50Y76 LUT6 (Prop_lut6_I3_O) 0.124 7.248 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, routed) 0.619 7.866 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + SLICE_X50Y76 LUT6 (Prop_lut6_I5_O) 0.124 7.990 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, routed) 0.842 8.832 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + SLICE_X63Y77 LUT5 (Prop_lut5_I3_O) 0.124 8.956 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, routed) 0.899 9.854 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + SLICE_X66Y84 LUT6 (Prop_lut6_I0_O) 0.124 9.978 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, routed) 0.463 10.441 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + SLICE_X66Y84 LUT6 (Prop_lut6_I2_O) 0.124 10.565 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_34/O + net (fo=8, routed) 0.643 11.208 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[1] + SLICE_X65Y84 LUT6 (Prop_lut6_I3_O) 0.124 11.332 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40/O + net (fo=2, routed) 0.592 11.924 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_40_n_1 + SLICE_X67Y83 LUT6 (Prop_lut6_I5_O) 0.124 12.048 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30/O + net (fo=1, routed) 0.453 12.501 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_30_n_1 + SLICE_X66Y85 LUT5 (Prop_lut5_I2_O) 0.124 12.625 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16/O + net (fo=3, routed) 0.437 13.062 i_ariane/i_cva6/issue_stage_i/i_scoreboard/asid_to_be_flushed[0]_i_16_n_1 + SLICE_X65Y86 LUT6 (Prop_lut6_I2_O) 0.124 13.186 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_11/O + net (fo=1, routed) 0.582 13.768 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs2_valid + SLICE_X67Y82 LUT6 (Prop_lut6_I1_O) 0.124 13.892 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5/O + net (fo=2, routed) 0.574 14.466 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_5_n_1 + SLICE_X65Y82 LUT6 (Prop_lut6_I3_O) 0.124 14.590 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, routed) 0.819 15.409 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + SLICE_X58Y80 LUT5 (Prop_lut5_I0_O) 0.117 15.526 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[1][sbe][fu][3]_i_2/O + net (fo=3, routed) 0.680 16.206 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_n[1][sbe][fu][3] + SLICE_X57Y81 LUT6 (Prop_lut6_I2_O) 0.331 16.537 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9/O + net (fo=4, routed) 0.771 17.308 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_9_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I1_O) 0.124 17.432 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3/O + net (fo=6, routed) 0.877 18.310 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_3_n_1 + SLICE_X54Y82 LUT6 (Prop_lut6_I0_O) 0.124 18.434 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1/O + net (fo=5, routed) 0.446 18.880 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[2][sbe][rd][4]_i_1_n_1 + SLICE_X53Y82 FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, routed) 1.162 22.566 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -7.814 14.752 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, routed) 2.012 16.764 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.855 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=20574, routed) 1.458 18.313 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + SLICE_X53Y82 FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3]/C + clock pessimism 0.567 18.880 + clock uncertainty -0.079 18.800 + SLICE_X53Y82 FDCE (Setup_fdce_C_CE) -0.205 18.595 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[2][sbe][rd][3] + ------------------------------------------------------------------- + required time 18.595 + arrival time -18.880 + ------------------------------------------------------------------- + slack -0.284 + + + + diff --git a/REPORT/reports_cva6_fpga_impl/cva6_fpga.utilization.rpt b/REPORT/reports_cva6_fpga_impl/cva6_fpga.utilization.rpt new file mode 100644 index 00000000..4045d710 --- /dev/null +++ b/REPORT/reports_cva6_fpga_impl/cva6_fpga.utilization.rpt @@ -0,0 +1,841 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:29:31 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : report_utilization -hierarchical -file reports_cva6_fpga_impl/cva6_fpga.utilization.rpt +| Design : cva6_zybo_z7_20 +| Device : xc7z020clg400-1 +| Speed File : -1 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++-----------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++-----------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| cva6_zybo_z7_20 | (top) | 35810 | 34952 | 818 | 40 | 19076 | 66 | 1 | 4 | +| (cva6_zybo_z7_20) | (top) | 503 | 27 | 476 | 0 | 3 | 0 | 0 | 0 | +| i_ariane | ariane | 24567 | 24301 | 266 | 0 | 9854 | 16 | 1 | 4 | +| gen_example_coprocessor.i_cvxif_coprocessor | cvxif_example_coprocessor | 15056 | 15006 | 50 | 0 | 5169 | 0 | 0 | 0 | +| (gen_example_coprocessor.i_cvxif_coprocessor) | cvxif_example_coprocessor | 2300 | 2300 | 0 | 0 | 2720 | 0 | 0 | 0 | +| fifo_commit_i | fifo_v3__parameterized6 | 172 | 122 | 50 | 0 | 10 | 0 | 0 | 0 | +| (fifo_commit_i) | fifo_v3__parameterized6 | 42 | 42 | 0 | 0 | 10 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized6 | 130 | 80 | 50 | 0 | 0 | 0 | 0 | 0 | +| inputs_registers | cvxif_registers__parameterized0 | 5182 | 5182 | 0 | 0 | 1220 | 0 | 0 | 0 | +| weights_registers | cvxif_registers | 7713 | 7713 | 0 | 0 | 1219 | 0 | 0 | 0 | +| i_cva6 | cva6 | 9512 | 9296 | 216 | 0 | 4685 | 16 | 1 | 4 | +| (i_cva6) | cva6 | 60 | 0 | 60 | 0 | 0 | 0 | 0 | 0 | +| csr_regfile_i | csr_regfile | 287 | 287 | 0 | 0 | 706 | 0 | 0 | 0 | +| ex_stage_i | ex_stage | 2587 | 2587 | 0 | 0 | 1815 | 4 | 0 | 4 | +| (ex_stage_i) | ex_stage | 0 | 0 | 0 | 0 | 34 | 0 | 0 | 0 | +| csr_buffer_i | csr_buffer | 622 | 622 | 0 | 0 | 13 | 0 | 0 | 0 | +| gen_cvxif.cvxif_fu_i | cvxif_fu | 1 | 1 | 0 | 0 | 35 | 0 | 0 | 0 | +| i_mult | mult | 290 | 290 | 0 | 0 | 155 | 0 | 0 | 4 | +| i_div | serdiv | 191 | 191 | 0 | 0 | 111 | 0 | 0 | 0 | +| i_multiplier | multiplier | 99 | 99 | 0 | 0 | 44 | 0 | 0 | 4 | +| lsu_i | load_store_unit | 1674 | 1674 | 0 | 0 | 1578 | 4 | 0 | 0 | +| gen_mmu_sv32.i_cva6_mmu | cva6_mmu_sv32 | 836 | 836 | 0 | 0 | 589 | 4 | 0 | 0 | +| (gen_mmu_sv32.i_cva6_mmu) | cva6_mmu_sv32 | 25 | 25 | 0 | 0 | 96 | 0 | 0 | 0 | +| i_dtlb | cva6_tlb_sv32 | 94 | 94 | 0 | 0 | 99 | 0 | 0 | 0 | +| i_itlb | cva6_tlb_sv32_335 | 99 | 99 | 0 | 0 | 95 | 0 | 0 | 0 | +| i_ptw | cva6_ptw_sv32 | 373 | 373 | 0 | 0 | 105 | 0 | 0 | 0 | +| i_shared_tlb | cva6_shared_tlb_sv32 | 245 | 245 | 0 | 0 | 194 | 4 | 0 | 0 | +| (i_shared_tlb) | cva6_shared_tlb_sv32 | 37 | 37 | 0 | 0 | 186 | 0 | 0 | 0 | +| gen_sram[0].pte_sram | sram__parameterized3 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper__parameterized0_343 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64__parameterized0_344 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[0].tag_sram | sram__parameterized2 | 30 | 30 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper__parameterized0_341 | 30 | 30 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64__parameterized0_342 | 30 | 30 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[1].pte_sram | sram__parameterized3_336 | 26 | 26 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper__parameterized0_339 | 26 | 26 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64__parameterized0_340 | 26 | 26 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[1].tag_sram | sram__parameterized2_337 | 39 | 39 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_lfsr | lfsr_338 | 113 | 113 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_load_unit | load_unit | 77 | 77 | 0 | 0 | 63 | 0 | 0 | 0 | +| i_pipe_reg_load | shift_reg | 184 | 184 | 0 | 0 | 72 | 0 | 0 | 0 | +| i_store_unit | store_unit | 334 | 334 | 0 | 0 | 686 | 0 | 0 | 0 | +| (i_store_unit) | store_unit | 10 | 10 | 0 | 0 | 46 | 0 | 0 | 0 | +| i_amo_buffer | amo_buffer | 67 | 67 | 0 | 0 | 74 | 0 | 0 | 0 | +| i_amo_fifo | fifo_v3__parameterized13 | 67 | 67 | 0 | 0 | 74 | 0 | 0 | 0 | +| (i_amo_fifo) | fifo_v3__parameterized13 | 27 | 27 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized13 | 40 | 40 | 0 | 0 | 72 | 0 | 0 | 0 | +| store_buffer_i | store_buffer | 257 | 257 | 0 | 0 | 566 | 0 | 0 | 0 | +| lsu_bypass_i | lsu_bypass | 243 | 243 | 0 | 0 | 168 | 0 | 0 | 0 | +| gen_cache_wt.i_cache_subsystem | wt_cache_subsystem | 2393 | 2303 | 90 | 0 | 857 | 12 | 0 | 0 | +| (gen_cache_wt.i_cache_subsystem) | wt_cache_subsystem | 284 | 282 | 2 | 0 | 0 | 0 | 0 | 0 | +| i_adapter | wt_axi_adapter | 731 | 643 | 88 | 0 | 315 | 0 | 0 | 0 | +| (i_adapter) | wt_axi_adapter | 143 | 143 | 0 | 0 | 277 | 0 | 0 | 0 | +| i_axi_shim | axi_shim | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_b_fifo | fifo_v3__parameterized10 | 31 | 27 | 4 | 0 | 7 | 0 | 0 | 0 | +| (i_b_fifo) | fifo_v3__parameterized10 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized10 | 22 | 18 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_dcache_data_fifo | fifo_v3__parameterized9 | 497 | 441 | 56 | 0 | 4 | 0 | 0 | 0 | +| (i_dcache_data_fifo) | fifo_v3__parameterized9 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized9 | 495 | 439 | 56 | 0 | 0 | 0 | 0 | 0 | +| i_icache_data_fifo | fifo_v3__parameterized8 | 24 | 0 | 24 | 0 | 4 | 0 | 0 | 0 | +| (i_icache_data_fifo) | fifo_v3__parameterized8 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized8 | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| i_rd_dcache_id | fifo_v3__parameterized7_331 | 9 | 7 | 2 | 0 | 7 | 0 | 0 | 0 | +| (i_rd_dcache_id) | fifo_v3__parameterized7_331 | 4 | 4 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized7_334 | 5 | 3 | 2 | 0 | 0 | 0 | 0 | 0 | +| i_rd_icache_id | fifo_v3__parameterized7_332 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| i_rr_arb_tree | rr_arb_tree__parameterized7 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_wr_dcache_id | fifo_v3__parameterized7_333 | 14 | 12 | 2 | 0 | 7 | 0 | 0 | 0 | +| (i_wr_dcache_id) | fifo_v3__parameterized7_333 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized7 | 6 | 4 | 2 | 0 | 0 | 0 | 0 | 0 | +| i_cva6_icache | cva6_icache | 177 | 177 | 0 | 0 | 80 | 6 | 0 | 0 | +| (i_cva6_icache) | cva6_icache | 20 | 20 | 0 | 0 | 72 | 0 | 0 | 0 | +| gen_sram[0].data_sram | sram__parameterized0 | 34 | 34 | 0 | 0 | 0 | 2 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_327 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_330 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[1].i_tc_sram_wrapper | tc_sram_wrapper_328 | 34 | 34 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_329 | 34 | 34 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[0].tag_sram | sram_315 | 43 | 43 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_325 | 43 | 43 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_326 | 43 | 43 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[1].data_sram | sram__parameterized0_316 | 49 | 49 | 0 | 0 | 0 | 2 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_321 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_324 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[1].i_tc_sram_wrapper | tc_sram_wrapper_322 | 49 | 49 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_323 | 49 | 49 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[1].tag_sram | sram_317 | 28 | 28 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_319 | 28 | 28 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_320 | 28 | 28 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_lfsr | lfsr_318 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_wt_dcache | wt_dcache | 1204 | 1204 | 0 | 0 | 462 | 6 | 0 | 0 | +| gen_rd_ports[0].i_wt_dcache_ctrl | wt_dcache_ctrl | 55 | 55 | 0 | 0 | 40 | 0 | 0 | 0 | +| gen_rd_ports[1].i_wt_dcache_ctrl | wt_dcache_ctrl_299 | 53 | 53 | 0 | 0 | 44 | 0 | 0 | 0 | +| gen_rd_ports[2].i_wt_dcache_ctrl | wt_dcache_ctrl_300 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | +| i_wt_dcache_mem | wt_dcache_mem | 151 | 151 | 0 | 0 | 15 | 6 | 0 | 0 | +| (i_wt_dcache_mem) | wt_dcache_mem | 11 | 11 | 0 | 0 | 13 | 0 | 0 | 0 | +| gen_data_banks[0].i_data_sram | sram__parameterized1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_313 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_314 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_data_banks[1].i_data_sram | sram__parameterized1_301 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_311 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_312 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_data_banks[2].i_data_sram | sram__parameterized1_302 | 50 | 50 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_309 | 50 | 50 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_310 | 50 | 50 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_data_banks[3].i_data_sram | sram__parameterized1_303 | 38 | 38 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_307 | 38 | 38 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_308 | 38 | 38 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_tag_srams[0].i_tag_sram | sram | 10 | 10 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_305 | 10 | 10 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_306 | 10 | 10 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_tag_srams[1].i_tag_sram | sram_304 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_rr_arb_tree | rr_arb_tree__parameterized6 | 26 | 26 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_wt_dcache_missunit | wt_dcache_missunit | 242 | 242 | 0 | 0 | 118 | 0 | 0 | 0 | +| (i_wt_dcache_missunit) | wt_dcache_missunit | 126 | 126 | 0 | 0 | 62 | 0 | 0 | 0 | +| i_exp_backoff | exp_backoff | 28 | 28 | 0 | 0 | 48 | 0 | 0 | 0 | +| i_lfsr_inv | lfsr | 88 | 88 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_wt_dcache_wbuffer | wt_dcache_wbuffer | 696 | 696 | 0 | 0 | 238 | 0 | 0 | 0 | +| (i_wt_dcache_wbuffer) | wt_dcache_wbuffer | 489 | 489 | 0 | 0 | 219 | 0 | 0 | 0 | +| i_clean_rr | rr_arb_tree__parameterized5 | 44 | 44 | 0 | 0 | 1 | 0 | 0 | 0 | +| i_dirty_rr | rr_arb_tree__parameterized4 | 112 | 112 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_rtrn_id_fifo | fifo_v3__parameterized7 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | +| i_tx_id_rr | rr_arb_tree__parameterized3 | 16 | 16 | 0 | 0 | 7 | 0 | 0 | 0 | +| i_frontend | frontend | 507 | 485 | 22 | 0 | 299 | 0 | 1 | 0 | +| (i_frontend) | frontend | 1 | 1 | 0 | 0 | 136 | 0 | 0 | 0 | +| btb_gen.i_btb | btb | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| gen_fpga_btb.gen_btb_ram[0].i_btb_ram | SyncDpRam | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| i_instr_queue | instr_queue | 133 | 111 | 22 | 0 | 47 | 0 | 0 | 0 | +| (i_instr_queue) | instr_queue | 3 | 3 | 0 | 0 | 33 | 0 | 0 | 0 | +| gen_instr_fifo[0].i_fifo_instr_data | fifo_v3__parameterized11 | 42 | 42 | 0 | 0 | 7 | 0 | 0 | 0 | +| i_fifo_address | fifo_v3__parameterized12 | 92 | 70 | 22 | 0 | 7 | 0 | 0 | 0 | +| (i_fifo_address) | fifo_v3__parameterized12 | 15 | 15 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized12 | 77 | 55 | 22 | 0 | 0 | 0 | 0 | 0 | +| i_instr_realign | instr_realign | 360 | 360 | 0 | 0 | 50 | 0 | 0 | 0 | +| ras_gen.i_ras | ras | 17 | 17 | 0 | 0 | 66 | 0 | 0 | 0 | +| id_stage_i | id_stage | 238 | 238 | 0 | 0 | 168 | 0 | 0 | 0 | +| issue_stage_i | issue_stage | 3444 | 3400 | 44 | 0 | 840 | 0 | 0 | 0 | +| i_issue_read_operands | issue_read_operands | 1666 | 1622 | 44 | 0 | 218 | 0 | 0 | 0 | +| (i_issue_read_operands) | issue_read_operands | 1622 | 1622 | 0 | 0 | 218 | 0 | 0 | 0 | +| gen_fpga_regfile.i_ariane_regfile_fpga | ariane_regfile_fpga | 44 | 0 | 44 | 0 | 0 | 0 | 0 | 0 | +| i_scoreboard | scoreboard | 1778 | 1778 | 0 | 0 | 622 | 0 | 0 | 0 | +| i_ariane_peripherals | ariane_peripherals | 2295 | 2295 | 0 | 0 | 2426 | 0 | 0 | 0 | +| gen_timer.i_axi2apb_64_32_timer | axi2apb_64_32 | 301 | 301 | 0 | 0 | 112 | 0 | 0 | 0 | +| (gen_timer.i_axi2apb_64_32_timer) | axi2apb_64_32 | 16 | 16 | 0 | 0 | 92 | 0 | 0 | 0 | +| slave_ar_buffer_i | axi_ar_buffer_274 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_295 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_296 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_297 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_298 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_aw_buffer_i | axi_aw_buffer_275 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_291 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_292 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_293 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_294 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_b_buffer_i | axi_b_buffer_276 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized2_287 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized2_288 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized4_289 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized17_290 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_r_buffer_i | axi_r_buffer_277 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized1_283 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized1_284 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized3_285 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized16_286 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_w_buffer_i | axi_w_buffer_278 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized0_279 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized0_280 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized2_281 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized15_282 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_timer.i_timer | apb_timer | 267 | 267 | 0 | 0 | 256 | 0 | 0 | 0 | +| TIMER_GEN[0].timer_i | timer | 124 | 124 | 0 | 0 | 128 | 0 | 0 | 0 | +| TIMER_GEN[1].timer_i | timer_273 | 143 | 143 | 0 | 0 | 128 | 0 | 0 | 0 | +| gen_uart.i_apb_uart | apb_uart | 769 | 769 | 0 | 0 | 1477 | 0 | 0 | 0 | +| (gen_uart.i_apb_uart) | apb_uart | 17 | 17 | 0 | 0 | 102 | 0 | 0 | 0 | +| UART_BG16 | uart_baudgen | 15 | 15 | 0 | 0 | 17 | 0 | 0 | 0 | +| UART_BG2 | slib_clock_div | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| UART_BIDET | slib_edge_detect | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_ED_CTS | slib_edge_detect_262 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_ED_DCD | slib_edge_detect_263 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_ED_DSR | slib_edge_detect_264 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_ED_RI | slib_edge_detect_265 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_FEDET | slib_edge_detect_266 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_IF_CTS | slib_input_filter | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| UART_IF_DCD | slib_input_filter_267 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| UART_IF_DSR | slib_input_filter_268 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| UART_IF_RI | slib_input_filter_269 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| UART_IIC | uart_interrupt | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | +| UART_IIC_THRE_ED | slib_edge_detect_270 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_IS_SIN | slib_input_sync | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| UART_PEDET | slib_edge_detect_271 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_RCLK | slib_edge_detect_272 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_RX | uart_receiver | 49 | 49 | 0 | 0 | 35 | 0 | 0 | 0 | +| (UART_RX) | uart_receiver | 13 | 13 | 0 | 0 | 21 | 0 | 0 | 0 | +| RX_BRC | slib_counter | 13 | 13 | 0 | 0 | 5 | 0 | 0 | 0 | +| RX_IFSB | slib_input_filter__parameterized2 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | +| RX_MVF | slib_mv_filter | 15 | 15 | 0 | 0 | 5 | 0 | 0 | 0 | +| UART_RXFF | slib_fifo__parameterized1 | 367 | 367 | 0 | 0 | 736 | 0 | 0 | 0 | +| UART_TX | uart_transmitter | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | +| UART_TXFF | slib_fifo | 278 | 278 | 0 | 0 | 540 | 0 | 0 | 0 | +| i_axi2apb_64_32_plic | axi2apb_64_32_230 | 530 | 530 | 0 | 0 | 164 | 0 | 0 | 0 | +| (i_axi2apb_64_32_plic) | axi2apb_64_32_230 | 80 | 80 | 0 | 0 | 144 | 0 | 0 | 0 | +| slave_ar_buffer_i | axi_ar_buffer_237 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_258 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_259 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_260 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_261 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_aw_buffer_i | axi_aw_buffer_238 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_254 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_255 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_256 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_257 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_b_buffer_i | axi_b_buffer_239 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized2_250 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized2_251 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized4_252 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized17_253 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_r_buffer_i | axi_r_buffer_240 | 82 | 82 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized1_246 | 82 | 82 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized1_247 | 82 | 82 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized3_248 | 82 | 82 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized16_249 | 82 | 82 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_w_buffer_i | axi_w_buffer_241 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized0_242 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized0_243 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized2_244 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized15_245 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi2apb_64_32_uart | axi2apb_64_32_231 | 156 | 156 | 0 | 0 | 64 | 0 | 0 | 0 | +| (i_axi2apb_64_32_uart) | axi2apb_64_32_231 | 15 | 15 | 0 | 0 | 44 | 0 | 0 | 0 | +| slave_ar_buffer_i | axi_ar_buffer | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_233 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_234 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_235 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_236 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_aw_buffer_i | axi_aw_buffer | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_b_buffer_i | axi_b_buffer | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized2 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized2 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized4 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized17 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_r_buffer_i | axi_r_buffer | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized1 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized1 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized3 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized16 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_w_buffer_i | axi_w_buffer | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized0 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized0 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized2 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized15 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_plic | plic_top | 276 | 276 | 0 | 0 | 353 | 0 | 0 | 0 | +| (i_plic) | plic_top | 147 | 147 | 0 | 0 | 282 | 0 | 0 | 0 | +| gen_target[0].i_target | rv_plic_target | 31 | 31 | 0 | 0 | 14 | 0 | 0 | 0 | +| gen_target[1].i_target | rv_plic_target_232 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_rv_plic_gateway | rv_plic_gateway | 87 | 87 | 0 | 0 | 53 | 0 | 0 | 0 | +| i_axi2rom | axi2mem__parameterized0 | 86 | 86 | 0 | 0 | 49 | 0 | 0 | 0 | +| i_axi_dwidth_converter_dm_master | xlnx_axi_dwidth_converter_dm_master | 380 | 341 | 0 | 39 | 396 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_top | 380 | 341 | 0 | 39 | 396 | 0 | 0 | 0 | +| gen_upsizer.gen_full_upsizer.axi_upsizer_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_axi_upsizer | 380 | 341 | 0 | 39 | 396 | 0 | 0 | 0 | +| USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axi_register_slice | 36 | 36 | 0 | 0 | 132 | 0 | 0 | 0 | +| r.r_pipe | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axic_register_slice__parameterized2 | 36 | 36 | 0 | 0 | 132 | 0 | 0 | 0 | +| USE_READ.gen_non_fifo_r_upsizer.read_data_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_r_upsizer | 56 | 56 | 0 | 0 | 18 | 0 | 0 | 0 | +| USE_READ.read_addr_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_a_upsizer__parameterized0 | 51 | 36 | 0 | 15 | 32 | 0 | 0 | 0 | +| (USE_READ.read_addr_inst) | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_a_upsizer__parameterized0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| GEN_CMD_QUEUE.cmd_queue | xlnx_axi_dwidth_converter_dm_master_generic_baseblocks_v2_1_1_command_fifo__parameterized0_1 | 41 | 26 | 0 | 15 | 23 | 0 | 0 | 0 | +| gen_id_queue.id_queue | xlnx_axi_dwidth_converter_dm_master_generic_baseblocks_v2_1_1_command_fifo_2 | 10 | 10 | 0 | 0 | 8 | 0 | 0 | 0 | +| USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_w_upsizer | 32 | 32 | 0 | 0 | 90 | 0 | 0 | 0 | +| USE_WRITE.write_addr_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_a_upsizer | 151 | 127 | 0 | 24 | 41 | 0 | 0 | 0 | +| (USE_WRITE.write_addr_inst) | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_a_upsizer | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| GEN_CMD_QUEUE.cmd_queue | xlnx_axi_dwidth_converter_dm_master_generic_baseblocks_v2_1_1_command_fifo__parameterized0 | 138 | 114 | 0 | 24 | 32 | 0 | 0 | 0 | +| gen_id_queue.id_queue | xlnx_axi_dwidth_converter_dm_master_generic_baseblocks_v2_1_1_command_fifo | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | +| si_register_slice_inst | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axi_register_slice__parameterized0 | 54 | 54 | 0 | 0 | 83 | 0 | 0 | 0 | +| ar.ar_pipe | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axic_register_slice__parameterized3 | 10 | 10 | 0 | 0 | 37 | 0 | 0 | 0 | +| aw.aw_pipe | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axic_register_slice__parameterized3_0 | 44 | 44 | 0 | 0 | 46 | 0 | 0 | 0 | +| i_axi_dwidth_converter_dm_slave | xlnx_axi_dwidth_converter_dm_slave | 543 | 503 | 40 | 0 | 509 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_top | 543 | 503 | 40 | 0 | 509 | 0 | 0 | 0 | +| gen_downsizer.gen_simple_downsizer.axi_downsizer_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_axi_downsizer | 543 | 503 | 40 | 0 | 509 | 0 | 0 | 0 | +| USE_READ.read_addr_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_a_downsizer__parameterized0 | 177 | 159 | 18 | 0 | 167 | 0 | 0 | 0 | +| (USE_READ.read_addr_inst) | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_a_downsizer__parameterized0 | 76 | 76 | 0 | 0 | 79 | 0 | 0 | 0 | +| cmd_queue | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_axic_fifo__parameterized0 | 103 | 85 | 18 | 0 | 88 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen__parameterized0 | 103 | 85 | 18 | 0 | 88 | 0 | 0 | 0 | +| (inst) | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen__parameterized0 | 53 | 53 | 0 | 0 | 0 | 0 | 0 | 0 | +| fifo_gen_inst | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9__parameterized0 | 50 | 32 | 18 | 0 | 88 | 0 | 0 | 0 | +| inst_fifo_gen | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9_synth__parameterized0 | 50 | 32 | 18 | 0 | 88 | 0 | 0 | 0 | +| gconvfifo.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_top__parameterized0 | 50 | 32 | 18 | 0 | 88 | 0 | 0 | 0 | +| grf.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_ramfifo__parameterized0 | 50 | 32 | 18 | 0 | 88 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | xlnx_axi_dwidth_converter_dm_slave_rd_logic_7 | 10 | 10 | 0 | 0 | 20 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | xlnx_axi_dwidth_converter_dm_slave_rd_fwft_13 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| grss.rsts | xlnx_axi_dwidth_converter_dm_slave_rd_status_flags_ss_14 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | xlnx_axi_dwidth_converter_dm_slave_rd_bin_cntr_15 | 3 | 3 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | xlnx_axi_dwidth_converter_dm_slave_wr_logic_8 | 14 | 14 | 0 | 0 | 12 | 0 | 0 | 0 | +| gwss.wsts | xlnx_axi_dwidth_converter_dm_slave_wr_status_flags_ss_11 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | xlnx_axi_dwidth_converter_dm_slave_wr_bin_cntr_12 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | xlnx_axi_dwidth_converter_dm_slave_memory__parameterized0_9 | 18 | 0 | 18 | 0 | 52 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | xlnx_axi_dwidth_converter_dm_slave_memory__parameterized0_9 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | +| gdm.dm_gen.dm | xlnx_axi_dwidth_converter_dm_slave_dmem__parameterized0_10 | 18 | 0 | 18 | 0 | 26 | 0 | 0 | 0 | +| rstblk | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | +| (rstblk) | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | xlnx_axi_dwidth_converter_dm_slave_xpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| USE_READ.read_data_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_r_downsizer | 48 | 48 | 0 | 0 | 76 | 0 | 0 | 0 | +| USE_WRITE.USE_SPLIT.write_resp_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_b_downsizer | 17 | 17 | 0 | 0 | 11 | 0 | 0 | 0 | +| USE_WRITE.write_addr_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_a_downsizer | 265 | 243 | 22 | 0 | 243 | 0 | 0 | 0 | +| (USE_WRITE.write_addr_inst) | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_a_downsizer | 113 | 113 | 0 | 0 | 111 | 0 | 0 | 0 | +| USE_B_CHANNEL.cmd_b_queue | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_axic_fifo | 50 | 46 | 4 | 0 | 46 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen | 50 | 46 | 4 | 0 | 46 | 0 | 0 | 0 | +| (inst) | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen | 14 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | +| fifo_gen_inst | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9 | 36 | 32 | 4 | 0 | 46 | 0 | 0 | 0 | +| inst_fifo_gen | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9_synth | 36 | 32 | 4 | 0 | 46 | 0 | 0 | 0 | +| gconvfifo.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_top | 36 | 32 | 4 | 0 | 46 | 0 | 0 | 0 | +| grf.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_ramfifo | 36 | 32 | 4 | 0 | 46 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | xlnx_axi_dwidth_converter_dm_slave_rd_logic_0 | 10 | 10 | 0 | 0 | 20 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | xlnx_axi_dwidth_converter_dm_slave_rd_fwft_4 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| grss.rsts | xlnx_axi_dwidth_converter_dm_slave_rd_status_flags_ss_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | xlnx_axi_dwidth_converter_dm_slave_rd_bin_cntr_6 | 3 | 3 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | xlnx_axi_dwidth_converter_dm_slave_wr_logic_1 | 14 | 14 | 0 | 0 | 12 | 0 | 0 | 0 | +| gwss.wsts | xlnx_axi_dwidth_converter_dm_slave_wr_status_flags_ss_2 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | xlnx_axi_dwidth_converter_dm_slave_wr_bin_cntr_3 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | xlnx_axi_dwidth_converter_dm_slave_memory | 4 | 0 | 4 | 0 | 10 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | xlnx_axi_dwidth_converter_dm_slave_memory | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gdm.dm_gen.dm | xlnx_axi_dwidth_converter_dm_slave_dmem | 4 | 0 | 4 | 0 | 5 | 0 | 0 | 0 | +| rstblk | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo__xdcDup__1 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | +| (rstblk) | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo__xdcDup__1 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | xlnx_axi_dwidth_converter_dm_slave_xpm_cdc_async_rst__3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| cmd_queue | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_axic_fifo__parameterized0__xdcDup__1 | 102 | 84 | 18 | 0 | 86 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen__parameterized0__xdcDup__1 | 102 | 84 | 18 | 0 | 86 | 0 | 0 | 0 | +| (inst) | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen__parameterized0__xdcDup__1 | 52 | 52 | 0 | 0 | 0 | 0 | 0 | 0 | +| fifo_gen_inst | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9__parameterized0__xdcDup__1 | 50 | 32 | 18 | 0 | 86 | 0 | 0 | 0 | +| inst_fifo_gen | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9_synth__parameterized0__xdcDup__1 | 50 | 32 | 18 | 0 | 86 | 0 | 0 | 0 | +| gconvfifo.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_top__parameterized0__xdcDup__1 | 50 | 32 | 18 | 0 | 86 | 0 | 0 | 0 | +| grf.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_ramfifo__parameterized0__xdcDup__1 | 50 | 32 | 18 | 0 | 86 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | xlnx_axi_dwidth_converter_dm_slave_rd_logic | 10 | 10 | 0 | 0 | 20 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | xlnx_axi_dwidth_converter_dm_slave_rd_fwft | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| grss.rsts | xlnx_axi_dwidth_converter_dm_slave_rd_status_flags_ss | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | xlnx_axi_dwidth_converter_dm_slave_rd_bin_cntr | 3 | 3 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | xlnx_axi_dwidth_converter_dm_slave_wr_logic | 14 | 14 | 0 | 0 | 12 | 0 | 0 | 0 | +| gwss.wsts | xlnx_axi_dwidth_converter_dm_slave_wr_status_flags_ss | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | xlnx_axi_dwidth_converter_dm_slave_wr_bin_cntr | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | xlnx_axi_dwidth_converter_dm_slave_memory__parameterized0 | 18 | 0 | 18 | 0 | 50 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | xlnx_axi_dwidth_converter_dm_slave_memory__parameterized0 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | +| gdm.dm_gen.dm | xlnx_axi_dwidth_converter_dm_slave_dmem__parameterized0 | 18 | 0 | 18 | 0 | 25 | 0 | 0 | 0 | +| rstblk | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo__xdcDup__2 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | +| (rstblk) | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo__xdcDup__2 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | xlnx_axi_dwidth_converter_dm_slave_xpm_cdc_async_rst__4 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| USE_WRITE.write_data_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_w_downsizer | 36 | 36 | 0 | 0 | 12 | 0 | 0 | 0 | +| i_axi_riscv_atomics | axi_riscv_atomics_wrap | 1283 | 1283 | 0 | 0 | 590 | 0 | 0 | 0 | +| i_atomics | axi_riscv_atomics | 1283 | 1283 | 0 | 0 | 590 | 0 | 0 | 0 | +| i_amos | axi_riscv_amos | 1031 | 1031 | 0 | 0 | 275 | 0 | 0 | 0 | +| i_lrsc | axi_riscv_lrsc | 252 | 252 | 0 | 0 | 315 | 0 | 0 | 0 | +| (i_lrsc) | axi_riscv_lrsc | 27 | 27 | 0 | 0 | 43 | 0 | 0 | 0 | +| i_art | axi_res_tbl | 225 | 225 | 0 | 0 | 272 | 0 | 0 | 0 | +| i_axi_xbar | axi_xbar_intf | 4592 | 4560 | 32 | 0 | 3939 | 0 | 0 | 0 | +| i_xbar | axi_xbar | 4592 | 4560 | 32 | 0 | 3939 | 0 | 0 | 0 | +| (i_xbar) | axi_xbar | 9 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_mst_port_mux[0].i_axi_mux | axi_mux | 320 | 320 | 0 | 0 | 512 | 0 | 0 | 0 | +| (gen_mst_port_mux[0].i_axi_mux) | axi_mux | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_216 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_217 | 34 | 34 | 0 | 0 | 86 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_229 | 34 | 34 | 0 | 0 | 86 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_218 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_219 | 122 | 122 | 0 | 0 | 112 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_228 | 122 | 122 | 0 | 0 | 112 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_220 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_227 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_221 | 97 | 97 | 0 | 0 | 138 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_226 | 97 | 97 | 0 | 0 | 138 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_222 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_222 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_225 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_223 | 40 | 40 | 0 | 0 | 148 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_224 | 40 | 40 | 0 | 0 | 148 | 0 | 0 | 0 | +| gen_mst_port_mux[1].i_axi_mux | axi_mux_0 | 21 | 21 | 0 | 0 | 22 | 0 | 0 | 0 | +| (gen_mst_port_mux[1].i_axi_mux) | axi_mux_0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_202 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_203 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_215 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_204 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_205 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_214 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_206 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_213 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_207 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_212 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_208 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_208 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_211 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_209 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_210 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mst_port_mux[2].i_axi_mux | axi_mux_1 | 35 | 35 | 0 | 0 | 27 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_190 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_191 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_201 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_192 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_193 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_200 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_194 | 14 | 14 | 0 | 0 | 10 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_199 | 14 | 14 | 0 | 0 | 10 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_195 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_198 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_196 | 10 | 10 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_196 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_197 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mst_port_mux[3].i_axi_mux | axi_mux_2 | 28 | 28 | 0 | 0 | 27 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_178 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_179 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_189 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_180 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_181 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_188 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_182 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_187 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_183 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_186 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_184 | 11 | 11 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_184 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_185 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mst_port_mux[4].i_axi_mux | axi_mux_3 | 315 | 315 | 0 | 0 | 378 | 0 | 0 | 0 | +| (gen_mst_port_mux[4].i_axi_mux) | axi_mux_3 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_164 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_165 | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_177 | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_166 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_167 | 21 | 21 | 0 | 0 | 40 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_176 | 21 | 21 | 0 | 0 | 40 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_168 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_175 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_169 | 170 | 170 | 0 | 0 | 142 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_174 | 170 | 170 | 0 | 0 | 142 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_170 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_170 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_173 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_171 | 75 | 75 | 0 | 0 | 148 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_172 | 75 | 75 | 0 | 0 | 148 | 0 | 0 | 0 | +| gen_mst_port_mux[5].i_axi_mux | axi_mux_4 | 115 | 115 | 0 | 0 | 218 | 0 | 0 | 0 | +| (gen_mst_port_mux[5].i_axi_mux) | axi_mux_4 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_150 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_151 | 17 | 17 | 0 | 0 | 24 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_163 | 17 | 17 | 0 | 0 | 24 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_152 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_153 | 22 | 22 | 0 | 0 | 40 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_162 | 22 | 22 | 0 | 0 | 40 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_154 | 6 | 6 | 0 | 0 | 12 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_161 | 6 | 6 | 0 | 0 | 12 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_155 | 17 | 17 | 0 | 0 | 54 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_160 | 17 | 17 | 0 | 0 | 54 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_156 | 10 | 10 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_156 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_159 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_157 | 39 | 39 | 0 | 0 | 76 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_158 | 39 | 39 | 0 | 0 | 76 | 0 | 0 | 0 | +| gen_mst_port_mux[6].i_axi_mux | axi_mux_5 | 274 | 274 | 0 | 0 | 494 | 0 | 0 | 0 | +| (gen_mst_port_mux[6].i_axi_mux) | axi_mux_5 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_136 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_137 | 45 | 45 | 0 | 0 | 82 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_149 | 45 | 45 | 0 | 0 | 82 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_138 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_139 | 51 | 51 | 0 | 0 | 98 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_148 | 51 | 51 | 0 | 0 | 98 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_140 | 13 | 13 | 0 | 0 | 12 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_147 | 13 | 13 | 0 | 0 | 12 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_141 | 79 | 79 | 0 | 0 | 142 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_146 | 79 | 79 | 0 | 0 | 142 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_142 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_142 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_145 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_143 | 75 | 75 | 0 | 0 | 148 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_144 | 75 | 75 | 0 | 0 | 148 | 0 | 0 | 0 | +| gen_mst_port_mux[7].i_axi_mux | axi_mux_6 | 136 | 136 | 0 | 0 | 376 | 0 | 0 | 0 | +| (gen_mst_port_mux[7].i_axi_mux) | axi_mux_6 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_122 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_123 | 19 | 19 | 0 | 0 | 40 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_135 | 19 | 19 | 0 | 0 | 40 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_124 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_125 | 23 | 23 | 0 | 0 | 40 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_134 | 23 | 23 | 0 | 0 | 40 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_126 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_133 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_127 | 38 | 38 | 0 | 0 | 138 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_132 | 38 | 38 | 0 | 0 | 138 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_128 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_128 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_131 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_129 | 38 | 38 | 0 | 0 | 138 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_130 | 38 | 38 | 0 | 0 | 138 | 0 | 0 | 0 | +| gen_mst_port_mux[8].i_axi_mux | axi_mux_7 | 319 | 319 | 0 | 0 | 240 | 0 | 0 | 0 | +| (gen_mst_port_mux[8].i_axi_mux) | axi_mux_7 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_108 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_109 | 28 | 28 | 0 | 0 | 32 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_121 | 28 | 28 | 0 | 0 | 32 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_110 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_111 | 22 | 22 | 0 | 0 | 46 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_120 | 22 | 22 | 0 | 0 | 46 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_112 | 82 | 82 | 0 | 0 | 8 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_119 | 82 | 82 | 0 | 0 | 8 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_113 | 168 | 168 | 0 | 0 | 138 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_118 | 168 | 168 | 0 | 0 | 138 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_114 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_114 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_117 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_115 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_116 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mst_port_mux[9].i_axi_mux | axi_mux_8 | 143 | 143 | 0 | 0 | 408 | 0 | 0 | 0 | +| (gen_mst_port_mux[9].i_axi_mux) | axi_mux_8 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6 | 19 | 19 | 0 | 0 | 42 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6 | 19 | 19 | 0 | 0 | 42 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4 | 19 | 19 | 0 | 0 | 58 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4 | 19 | 19 | 0 | 0 | 58 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5 | 9 | 9 | 0 | 0 | 12 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5 | 9 | 9 | 0 | 0 | 12 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7 | 41 | 41 | 0 | 0 | 138 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7 | 41 | 41 | 0 | 0 | 138 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4 | 10 | 10 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_106 | 41 | 41 | 0 | 0 | 146 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_107 | 41 | 41 | 0 | 0 | 146 | 0 | 0 | 0 | +| gen_slv_port_demux[0].i_axi_ar_decode | addr_decode | 267 | 267 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[0].i_axi_aw_decode | addr_decode_9 | 267 | 267 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[0].i_axi_demux | axi_demux | 679 | 679 | 0 | 0 | 568 | 0 | 0 | 0 | +| (gen_slv_port_demux[0].i_axi_demux) | axi_demux | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.gen_ar_id_counter.i_ar_id_counter | axi_demux_id_counters_58 | 24 | 24 | 0 | 0 | 48 | 0 | 0 | 0 | +| (gen_demux.gen_ar_id_counter.i_ar_id_counter) | axi_demux_id_counters_58 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_counters[0].i_in_flight_cnt | delta_counter_90 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[10].i_in_flight_cnt | delta_counter_91 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[11].i_in_flight_cnt | delta_counter_92 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[12].i_in_flight_cnt | delta_counter_93 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[13].i_in_flight_cnt | delta_counter_94 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[14].i_in_flight_cnt | delta_counter_95 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[15].i_in_flight_cnt | delta_counter_96 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[1].i_in_flight_cnt | delta_counter_97 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[2].i_in_flight_cnt | delta_counter_98 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[3].i_in_flight_cnt | delta_counter_99 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[4].i_in_flight_cnt | delta_counter_100 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[5].i_in_flight_cnt | delta_counter_101 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[6].i_in_flight_cnt | delta_counter_102 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[7].i_in_flight_cnt | delta_counter_103 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[8].i_in_flight_cnt | delta_counter_104 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[9].i_in_flight_cnt | delta_counter_105 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.gen_aw_id_counter.i_aw_id_counter | axi_demux_id_counters_59 | 12 | 12 | 0 | 0 | 48 | 0 | 0 | 0 | +| (gen_demux.gen_aw_id_counter.i_aw_id_counter) | axi_demux_id_counters_59 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_counters[0].i_in_flight_cnt | delta_counter_74 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[10].i_in_flight_cnt | delta_counter_75 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[11].i_in_flight_cnt | delta_counter_76 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[12].i_in_flight_cnt | delta_counter_77 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[13].i_in_flight_cnt | delta_counter_78 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[14].i_in_flight_cnt | delta_counter_79 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[15].i_in_flight_cnt | delta_counter_80 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[1].i_in_flight_cnt | delta_counter_81 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[2].i_in_flight_cnt | delta_counter_82 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[3].i_in_flight_cnt | delta_counter_83 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[4].i_in_flight_cnt | delta_counter_84 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[5].i_in_flight_cnt | delta_counter_85 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[6].i_in_flight_cnt | delta_counter_86 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[7].i_in_flight_cnt | delta_counter_87 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[8].i_in_flight_cnt | delta_counter_88 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[9].i_in_flight_cnt | delta_counter_89 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.i_ar_spill_reg | spill_register__parameterized2_60 | 90 | 90 | 0 | 0 | 90 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized2_73 | 90 | 90 | 0 | 0 | 90 | 0 | 0 | 0 | +| gen_demux.i_aw_spill_reg | spill_register_61 | 208 | 208 | 0 | 0 | 104 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable_72 | 208 | 208 | 0 | 0 | 104 | 0 | 0 | 0 | +| gen_demux.i_b_mux | rr_arb_tree_62 | 33 | 33 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_demux.i_b_spill_reg | spill_register__parameterized1_63 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized1_71 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gen_demux.i_r_mux | rr_arb_tree__parameterized0_64 | 127 | 127 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_demux.i_r_spill_reg | spill_register__parameterized3_65 | 130 | 130 | 0 | 0 | 140 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized3_70 | 130 | 130 | 0 | 0 | 140 | 0 | 0 | 0 | +| gen_demux.i_w_fifo | fifo_v3_66 | 23 | 23 | 0 | 0 | 6 | 0 | 0 | 0 | +| (gen_demux.i_w_fifo) | fifo_v3_66 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam_69 | 22 | 22 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_demux.i_w_spill_reg | spill_register__parameterized0_67 | 23 | 23 | 0 | 0 | 84 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_68 | 23 | 23 | 0 | 0 | 84 | 0 | 0 | 0 | +| gen_slv_port_demux[0].i_axi_err_slv | axi_err_slv | 105 | 89 | 16 | 0 | 48 | 0 | 0 | 0 | +| (gen_slv_port_demux[0].i_axi_err_slv) | axi_err_slv | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| i_atop_filter | axi_atop_filter_46 | 50 | 50 | 0 | 0 | 21 | 0 | 0 | 0 | +| (i_atop_filter) | axi_atop_filter_46 | 37 | 37 | 0 | 0 | 19 | 0 | 0 | 0 | +| r_resp_cmd | stream_register_55 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_fifo | fifo_v2_56 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized0_57 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_b_fifo | fifo_v3__parameterized2_47 | 10 | 6 | 4 | 0 | 4 | 0 | 0 | 0 | +| (i_b_fifo) | fifo_v3__parameterized2_47 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized2_54 | 6 | 2 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_r_counter | counter_48 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_counter | delta_counter__parameterized0_53 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_r_fifo | fifo_v3__parameterized3_49 | 15 | 7 | 8 | 0 | 7 | 0 | 0 | 0 | +| (i_r_fifo) | fifo_v3__parameterized3_49 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized3_52 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| i_w_fifo | fifo_v3__parameterized1_50 | 19 | 15 | 4 | 0 | 7 | 0 | 0 | 0 | +| (i_w_fifo) | fifo_v3__parameterized1_50 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized1_51 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[1].i_axi_ar_decode | addr_decode_10 | 252 | 252 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[1].i_axi_aw_decode | addr_decode_11 | 252 | 252 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[1].i_axi_demux | axi_demux_12 | 1032 | 1032 | 0 | 0 | 575 | 0 | 0 | 0 | +| (gen_slv_port_demux[1].i_axi_demux) | axi_demux_12 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.gen_ar_id_counter.i_ar_id_counter | axi_demux_id_counters | 17 | 17 | 0 | 0 | 36 | 0 | 0 | 0 | +| (gen_demux.gen_ar_id_counter.i_ar_id_counter) | axi_demux_id_counters | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_counters[0].i_in_flight_cnt | delta_counter_30 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[10].i_in_flight_cnt | delta_counter_31 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[11].i_in_flight_cnt | delta_counter_32 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[12].i_in_flight_cnt | delta_counter_33 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[13].i_in_flight_cnt | delta_counter_34 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[14].i_in_flight_cnt | delta_counter_35 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[15].i_in_flight_cnt | delta_counter_36 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[1].i_in_flight_cnt | delta_counter_37 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[2].i_in_flight_cnt | delta_counter_38 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[3].i_in_flight_cnt | delta_counter_39 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[4].i_in_flight_cnt | delta_counter_40 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[5].i_in_flight_cnt | delta_counter_41 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[6].i_in_flight_cnt | delta_counter_42 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[7].i_in_flight_cnt | delta_counter_43 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[8].i_in_flight_cnt | delta_counter_44 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[9].i_in_flight_cnt | delta_counter_45 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.gen_aw_id_counter.i_aw_id_counter | axi_demux_id_counters_14 | 17 | 17 | 0 | 0 | 36 | 0 | 0 | 0 | +| (gen_demux.gen_aw_id_counter.i_aw_id_counter) | axi_demux_id_counters_14 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_counters[0].i_in_flight_cnt | delta_counter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[10].i_in_flight_cnt | delta_counter_15 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[11].i_in_flight_cnt | delta_counter_16 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[12].i_in_flight_cnt | delta_counter_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[13].i_in_flight_cnt | delta_counter_18 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[14].i_in_flight_cnt | delta_counter_19 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[15].i_in_flight_cnt | delta_counter_20 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[1].i_in_flight_cnt | delta_counter_21 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[2].i_in_flight_cnt | delta_counter_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[3].i_in_flight_cnt | delta_counter_23 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[4].i_in_flight_cnt | delta_counter_24 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[5].i_in_flight_cnt | delta_counter_25 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[6].i_in_flight_cnt | delta_counter_26 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[7].i_in_flight_cnt | delta_counter_27 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[8].i_in_flight_cnt | delta_counter_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[9].i_in_flight_cnt | delta_counter_29 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.i_ar_spill_reg | spill_register__parameterized2 | 219 | 219 | 0 | 0 | 81 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized2 | 219 | 219 | 0 | 0 | 81 | 0 | 0 | 0 | +| gen_demux.i_aw_spill_reg | spill_register | 134 | 134 | 0 | 0 | 96 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable | 134 | 134 | 0 | 0 | 96 | 0 | 0 | 0 | +| gen_demux.i_b_mux | rr_arb_tree | 33 | 33 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_demux.i_b_spill_reg | spill_register__parameterized1 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized1 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.i_r_mux | rr_arb_tree__parameterized0 | 136 | 136 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_demux.i_r_spill_reg | spill_register__parameterized3 | 39 | 39 | 0 | 0 | 132 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized3 | 39 | 39 | 0 | 0 | 132 | 0 | 0 | 0 | +| gen_demux.i_w_fifo | fifo_v3 | 23 | 23 | 0 | 0 | 6 | 0 | 0 | 0 | +| (gen_demux.i_w_fifo) | fifo_v3 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam | 22 | 22 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_demux.i_w_spill_reg | spill_register__parameterized0 | 409 | 409 | 0 | 0 | 152 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0 | 409 | 409 | 0 | 0 | 152 | 0 | 0 | 0 | +| gen_slv_port_demux[1].i_axi_err_slv | axi_err_slv_13 | 99 | 83 | 16 | 0 | 46 | 0 | 0 | 0 | +| (gen_slv_port_demux[1].i_axi_err_slv) | axi_err_slv_13 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| i_atop_filter | axi_atop_filter | 44 | 44 | 0 | 0 | 19 | 0 | 0 | 0 | +| (i_atop_filter) | axi_atop_filter | 32 | 32 | 0 | 0 | 17 | 0 | 0 | 0 | +| r_resp_cmd | stream_register | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_fifo | fifo_v2 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized0 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_b_fifo | fifo_v3__parameterized2 | 10 | 6 | 4 | 0 | 4 | 0 | 0 | 0 | +| (i_b_fifo) | fifo_v3__parameterized2 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized2 | 6 | 2 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_r_counter | counter | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_counter | delta_counter__parameterized0 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_r_fifo | fifo_v3__parameterized3 | 17 | 9 | 8 | 0 | 7 | 0 | 0 | 0 | +| (i_r_fifo) | fifo_v3__parameterized3 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized3 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| i_w_fifo | fifo_v3__parameterized1 | 17 | 13 | 4 | 0 | 7 | 0 | 0 | 0 | +| (i_w_fifo) | fifo_v3__parameterized1 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized1 | 10 | 6 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_bootrom | bootrom_32 | 65 | 65 | 0 | 0 | 9 | 2 | 0 | 0 | +| i_clint | clint | 182 | 182 | 0 | 0 | 153 | 0 | 0 | 0 | +| (i_clint) | clint | 32 | 32 | 0 | 0 | 129 | 0 | 0 | 0 | +| axi_lite_interface_i | axi_lite_interface | 150 | 150 | 0 | 0 | 21 | 0 | 0 | 0 | +| i_sync_edge | clint_sync_wedge | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| (i_sync_edge) | clint_sync_wedge | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| i_sync | clint_sync | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_dm_axi2mem | axi2mem | 268 | 268 | 0 | 0 | 44 | 0 | 0 | 0 | +| i_dm_axi_master | axi_adapter | 65 | 65 | 0 | 0 | 40 | 0 | 0 | 0 | +| i_dm_top | dm_top | 497 | 497 | 0 | 0 | 613 | 0 | 0 | 0 | +| i_dm_csrs | dm_csrs | 363 | 363 | 0 | 0 | 535 | 0 | 0 | 0 | +| (i_dm_csrs) | dm_csrs | 243 | 243 | 0 | 0 | 531 | 0 | 0 | 0 | +| i_fifo | fifo_v2__parameterized0 | 120 | 120 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized5 | 120 | 120 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_dm_mem | dm_mem | 94 | 94 | 0 | 0 | 75 | 0 | 0 | 0 | +| (i_dm_mem) | dm_mem | 8 | 8 | 0 | 0 | 70 | 0 | 0 | 0 | +| gen_rom_snd_scratch.i_debug_rom | debug_rom | 86 | 86 | 0 | 0 | 5 | 0 | 0 | 0 | +| i_dm_sba | dm_sba | 40 | 40 | 0 | 0 | 3 | 0 | 0 | 0 | +| i_dmi_jtag | dmi_jtag | 489 | 489 | 0 | 0 | 340 | 0 | 0 | 0 | +| (i_dmi_jtag) | dmi_jtag | 1 | 1 | 0 | 0 | 84 | 0 | 0 | 0 | +| i_dmi_cdc | dmi_cdc | 364 | 364 | 0 | 0 | 164 | 0 | 0 | 0 | +| i_cdc_req | cdc_2phase | 321 | 321 | 0 | 0 | 89 | 0 | 0 | 0 | +| i_dst | cdc_2phase_dst | 318 | 318 | 0 | 0 | 45 | 0 | 0 | 0 | +| i_src | cdc_2phase_src | 3 | 3 | 0 | 0 | 44 | 0 | 0 | 0 | +| i_cdc_resp | cdc_2phase__parameterized0 | 43 | 43 | 0 | 0 | 75 | 0 | 0 | 0 | +| i_dst | cdc_2phase_dst__parameterized0 | 39 | 39 | 0 | 0 | 38 | 0 | 0 | 0 | +| i_src | cdc_2phase_src__parameterized0 | 4 | 4 | 0 | 0 | 37 | 0 | 0 | 0 | +| i_dmi_jtag_tap | dmi_jtag_tap | 124 | 124 | 0 | 0 | 92 | 0 | 0 | 0 | +| i_rstgen_main | rstgen | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_rstgen_bypass | rstgen_bypass | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_xlnx_blk_mem_gen | xlnx_blk_mem_gen | 369 | 364 | 4 | 1 | 107 | 48 | 0 | 0 | +| U0 | xlnx_blk_mem_gen_blk_mem_gen_v8_4_7 | 369 | 364 | 4 | 1 | 107 | 48 | 0 | 0 | +| inst_blk_mem_gen | xlnx_blk_mem_gen_blk_mem_gen_v8_4_7_synth | 369 | 364 | 4 | 1 | 107 | 48 | 0 | 0 | +| gnbram.gaxibmg.axi_blk_mem_gen | xlnx_blk_mem_gen_blk_mem_gen_top | 181 | 180 | 0 | 1 | 11 | 48 | 0 | 0 | +| valid.cstr | xlnx_blk_mem_gen_blk_mem_gen_generic_cstr | 181 | 180 | 0 | 1 | 11 | 48 | 0 | 0 | +| has_mux_b.B | xlnx_blk_mem_gen_blk_mem_gen_mux__parameterized0 | 128 | 128 | 0 | 0 | 3 | 0 | 0 | 0 | +| ramloop[0].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | +| (ramloop[0].ram.r) | xlnx_blk_mem_gen_blk_mem_gen_prim_width | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[10].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized9 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized9 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[11].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized10 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized10 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[12].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized11 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized11 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[13].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized12 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized12 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[14].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized13 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized13 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[15].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized14 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized14 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[16].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized15 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized15 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[17].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized16 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized16 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[18].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized17 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized17 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[19].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized18 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized18 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[1].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[20].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized19 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized19 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[21].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized20 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized20 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[22].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized21 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized21 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[23].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized22 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized22 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[24].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized23 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized23 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[25].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized24 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized24 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[26].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized25 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized25 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[27].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized26 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized26 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[28].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized27 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized27 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[29].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized28 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized28 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[2].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[30].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized29 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized29 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[31].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized30 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized30 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[32].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized31 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized31 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[33].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized32 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized32 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[34].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized33 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized33 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[35].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized34 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized34 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[36].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized35 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized35 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[37].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized36 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized36 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[38].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized37 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized37 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[39].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized38 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized38 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[3].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized2 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized2 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[40].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized39 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized39 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[41].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized40 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized40 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[42].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized41 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized41 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[43].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized42 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized42 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[44].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized43 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized43 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[45].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized44 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized44 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[46].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized45 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | +| (ramloop[46].ram.r) | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized45 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized45 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[47].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized46 | 6 | 5 | 0 | 1 | 6 | 1 | 0 | 0 | +| (ramloop[47].ram.r) | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized46 | 3 | 2 | 0 | 1 | 6 | 0 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized46 | 3 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[4].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized3 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized3 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[5].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized4 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized4 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[6].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized5 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized5 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[7].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized6 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized6 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[8].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized7 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized7 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[9].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized8 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized8 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | +| gnbram.gaxibmg.axi_rd_sm | xlnx_blk_mem_gen_blk_mem_axi_read_wrapper | 105 | 105 | 0 | 0 | 45 | 0 | 0 | 0 | +| (gnbram.gaxibmg.axi_rd_sm) | xlnx_blk_mem_gen_blk_mem_axi_read_wrapper | 8 | 8 | 0 | 0 | 39 | 0 | 0 | 0 | +| axi_read_fsm | xlnx_blk_mem_gen_blk_mem_axi_read_fsm | 97 | 97 | 0 | 0 | 6 | 0 | 0 | 0 | +| gnbram.gaxibmg.axi_wr_fsm | xlnx_blk_mem_gen_blk_mem_axi_write_wrapper | 83 | 79 | 4 | 0 | 51 | 0 | 0 | 0 | +| (gnbram.gaxibmg.axi_wr_fsm) | xlnx_blk_mem_gen_blk_mem_axi_write_wrapper | 28 | 24 | 4 | 0 | 47 | 0 | 0 | 0 | +| axi_wr_fsm | xlnx_blk_mem_gen_blk_mem_axi_write_fsm | 55 | 55 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_xlnx_clk_gen | xlnx_clk_gen | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | xlnx_clk_gen_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ++-----------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining + + diff --git a/REPORT/reports_cva6_fpga_synth/cva6_fpga.cdc.rpt b/REPORT/reports_cva6_fpga_synth/cva6_fpga.cdc.rpt new file mode 100644 index 00000000..6f20d9b8 --- /dev/null +++ b/REPORT/reports_cva6_fpga_synth/cva6_fpga.cdc.rpt @@ -0,0 +1,20 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:24:01 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : report_cdc -file reports_cva6_fpga_synth/cva6_fpga.cdc.rpt +| Design : cva6_zybo_z7_20 +| Device : 7z020-clg400 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +CDC Report + +Severity Source Clock Destination Clock CDC Type Exceptions Endpoints Safe Unsafe Unknown No ASYNC_REG +-------- --------------------- --------------------- ----------------------- ----------------------- --------- ---- ------ ------- ------------ +Critical input port clock tck No Common Primary Clock False Path 206 0 0 206 0 +Warning tck clk_out1_xlnx_clk_gen No Common Primary Clock None 43 43 0 0 1 +Warning clk_out1_xlnx_clk_gen tck No Common Primary Clock Max Delay Datapath Only 36 36 0 0 1 + diff --git a/REPORT/reports_cva6_fpga_synth/cva6_fpga.check_timing.rpt b/REPORT/reports_cva6_fpga_synth/cva6_fpga.check_timing.rpt new file mode 100644 index 00000000..0ae8a631 --- /dev/null +++ b/REPORT/reports_cva6_fpga_synth/cva6_fpga.check_timing.rpt @@ -0,0 +1,663 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:23:58 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : check_timing -verbose -file reports_cva6_fpga_synth/cva6_fpga.check_timing.rpt +| Design : cva6_zybo_z7_20 +| Device : 7z020-clg400 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (480) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (32) +5. checking no_input_delay (2) +6. checking no_output_delay (1) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (3) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (480) +-------------------------- + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][0]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][1]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][2]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][3]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][4]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][5]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[0][operation][6]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][0]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][1]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][2]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][3]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][4]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][5]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/ldbuf_q_reg[1][operation][6]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + There are 32 register/latch pins with no clock driven by root clock pin: i_ariane/i_cva6/gen_cache_wt.i_cache_subsystem/i_wt_dcache/gen_rd_ports[1].i_wt_dcache_ctrl/id_q_reg[0]/Q (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/G +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/G + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (32) +------------------------------------------------- + There are 32 pins that are not constrained for maximum delay. (HIGH) + +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[0]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[10]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[11]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[12]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[13]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[14]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[15]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[16]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[17]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[18]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[19]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[1]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[20]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[21]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[22]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[23]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[24]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[25]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[26]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[27]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[28]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[29]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[2]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[30]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[31]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[3]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[4]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[5]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[6]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[7]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[8]/D +i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/result_o_reg[9]/D + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (2) +------------------------------ + There are 2 input ports with no input delay specified. (HIGH) + +cpu_reset +rx + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (1) +------------------------------- + There is 1 port with no output delay specified. (HIGH) + +tx + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (3) +------------------------------------ + There are 3 input ports with partial input delay specified. (HIGH) + +tdi +tms +trst_n + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + diff --git a/REPORT/reports_cva6_fpga_synth/cva6_fpga.clock_interaction.rpt b/REPORT/reports_cva6_fpga_synth/cva6_fpga.clock_interaction.rpt new file mode 100644 index 00000000..3ce35058 --- /dev/null +++ b/REPORT/reports_cva6_fpga_synth/cva6_fpga.clock_interaction.rpt @@ -0,0 +1,26 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:24:03 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : report_clock_interaction -file reports_cva6_fpga_synth/cva6_fpga.clock_interaction.rpt +| Design : cva6_zybo_z7_20 +| Device : 7z020-clg400 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Interaction Report + +Clock Interaction Table +----------------------- + + WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock +From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints +--------------------- --------------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- ----------------------- +clk_out1_xlnx_clk_gen clk_out1_xlnx_clk_gen rise - rise -0.29 -5.87 20 61270 20.00 Clean Partial False Path +clk_out1_xlnx_clk_gen tck rise - rise 18.92 0.00 0 36 20.00 Ignored Max Delay Datapath Only +tck clk_out1_xlnx_clk_gen rise - rise 13.10 0.00 0 43 20.00 No Common Clock Timed (unsafe) +tck tck fall - rise 5.76 0.00 0 453 20.00 Clean Timed + + diff --git a/REPORT/reports_cva6_fpga_synth/cva6_fpga.timing.rpt b/REPORT/reports_cva6_fpga_synth/cva6_fpga.timing.rpt new file mode 100644 index 00000000..5f19cdc6 --- /dev/null +++ b/REPORT/reports_cva6_fpga_synth/cva6_fpga.timing.rpt @@ -0,0 +1,237 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:24:00 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : report_timing -nworst 1 -delay_type max -sort_by group -file reports_cva6_fpga_synth/cva6_fpga.timing.rpt +| Design : cva6_zybo_z7_20 +| Device : 7z020-clg400 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Report + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (MET) : 5.757ns (required time - arrival time) + Source: i_dmi_jtag/i_dmi_jtag_tap/td_o_reg/C + (rising edge-triggered cell FDCE clocked by tck' {rise@0.000ns fall@50.000ns period=100.000ns}) + Destination: tdo + (output port clocked by tck {rise@0.000ns fall@50.000ns period=100.000ns}) + Path Group: tck + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (MaxDelay Path 20.000ns) + Data Path Delay: 5.049ns (logic 4.249ns (84.161%) route 0.800ns (15.839%)) + Logic Levels: 1 (OBUF=1) + Output Delay: 5.000ns + Clock Path Skew: -3.693ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.000ns + Source Clock Delay (SCD): 3.693ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.501ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 1.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + Timing Exception: MaxDelay Path 20.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock tck fall edge) 0.000 0.000 f + H15 0.000 0.000 f tck (IN) + net (fo=0) 0.000 0.000 tck + H15 IBUF (Prop_ibuf_I_O) 1.500 1.500 f tck_IBUF_inst/O + net (fo=1, unplaced) 0.800 2.300 tck_IBUF + BUFG (Prop_bufg_I_O) 0.101 2.401 f tck_IBUF_BUFG_inst/O + net (fo=258, unplaced) 0.584 2.985 tck_IBUF_BUFG + LUT1 (Prop_lut1_I0_O) 0.124 3.109 r td_o_reg_i_2/O + net (fo=1, unplaced) 0.584 3.693 i_dmi_jtag/i_dmi_jtag_tap/tck_ni + FDCE r i_dmi_jtag/i_dmi_jtag_tap/td_o_reg/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.518 4.211 r i_dmi_jtag/i_dmi_jtag_tap/td_o_reg/Q + net (fo=1, unplaced) 0.800 5.011 tdo_OBUF + J15 OBUF (Prop_obuf_I_O) 3.731 8.742 r tdo_OBUF_inst/O + net (fo=0) 0.000 8.742 tdo + J15 r tdo (OUT) + ------------------------------------------------------------------- ------------------- + + max delay 20.000 20.000 + clock pessimism 0.000 20.000 + clock uncertainty -0.501 19.499 + output delay -5.000 14.499 + ------------------------------------------------------------------- + required time 14.499 + arrival time -8.742 + ------------------------------------------------------------------- + slack 5.757 + +Slack (MET) : 17.010ns (required time - arrival time) + Source: i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE + (recovery check against rising-edge clock clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 2.372ns (logic 0.773ns (32.589%) route 1.599ns (67.411%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk + FDRE r i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C + ------------------------------------------------------------------- ------------------- + FDRE (Prop_fdre_C_Q) 0.478 -1.091 f i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q + net (fo=2, unplaced) 0.752 -0.339 i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1] + LUT3 (Prop_lut3_I0_O) 0.295 -0.044 f i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O + net (fo=32, unplaced) 0.847 0.803 i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0 + FDPE f i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk + FDPE r i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDPE (Recov_fdpe_C_PRE) -0.394 17.812 i_axi_dwidth_converter_dm_slave/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg + ------------------------------------------------------------------- + required time 17.812 + arrival time -0.803 + ------------------------------------------------------------------- + slack 17.010 + + + + diff --git a/REPORT/reports_cva6_fpga_synth/cva6_fpga.timing_WORST_100.rpt b/REPORT/reports_cva6_fpga_synth/cva6_fpga.timing_WORST_100.rpt new file mode 100644 index 00000000..381c6c29 --- /dev/null +++ b/REPORT/reports_cva6_fpga_synth/cva6_fpga.timing_WORST_100.rpt @@ -0,0 +1,10617 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:23:59 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file reports_cva6_fpga_synth/cva6_fpga.timing_WORST_100.rpt +| Design : cva6_zybo_z7_20 +| Device : 7z020-clg400 +| Speed File : -1 PRODUCTION 1.12 2019-11-22 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------------------------------------ + +Timing Report + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 f i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 f i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 r i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + +Slack (VIOLATED) : -0.293ns (required time - arrival time) + Source: i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + (rising edge-triggered cell FDCE clocked by clk_out1_xlnx_clk_gen {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_out1_xlnx_clk_gen + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_out1_xlnx_clk_gen rise@20.000ns - clk_out1_xlnx_clk_gen rise@0.000ns) + Data Path Delay: 19.867ns (logic 3.549ns (17.864%) route 16.318ns (82.136%)) + Logic Levels: 23 (LUT4=1 LUT5=4 LUT6=18) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.245ns = ( 17.755 - 20.000 ) + Source Clock Delay (SCD): -1.569ns + Clock Pessimism Removal (CPR): 0.531ns + Clock Uncertainty: 0.079ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.142ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_out1_xlnx_clk_gen rise edge) + 0.000 0.000 r + K17 0.000 0.000 r clk_sys (IN) + net (fo=0) 0.000 0.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.584 2.059 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.113 -3.054 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.800 -2.254 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.101 -2.153 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.584 -1.569 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/C + ------------------------------------------------------------------- ------------------- + FDCE (Prop_fdce_C_Q) 0.478 -1.091 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep/Q + net (fo=110, unplaced) 1.067 -0.024 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_pointer_q_reg[0][1]_rep_n_1 + LUT6 (Prop_lut6_I0_O) 0.295 0.271 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[1]_i_6/O + net (fo=12, unplaced) 0.950 1.221 i_ariane/i_cva6/issue_stage_i/i_scoreboard/commit_sbe_cva6_cvxif[fu][0] + LUT4 (Prop_lut4_I1_O) 0.148 1.369 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15/O + net (fo=8, unplaced) 0.487 1.856 i_ariane/i_cva6/issue_stage_i/i_scoreboard/regfile_ram_block[0].mem_reg[0][0]_r1_0_31_0_5_i_15_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 1.980 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6/O + net (fo=6, unplaced) 1.143 3.123 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mstatus_q[mpp][1]_i_6_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 3.247 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17/O + net (fo=1, unplaced) 0.902 4.149 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_17_n_1 + LUT6 (Prop_lut6_I3_O) 0.124 4.273 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12/O + net (fo=2, unplaced) 0.913 5.186 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_12_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 5.310 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7/O + net (fo=1, unplaced) 0.449 5.759 i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_7_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 5.883 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/dpc_q[31]_i_4/O + net (fo=11, unplaced) 0.948 6.831 i_ariane/i_cva6/issue_stage_i/i_scoreboard/csr_regfile_i/debug_mode_d143_out + LUT6 (Prop_lut6_I0_O) 0.124 6.955 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/debug_mode_q_i_5/O + net (fo=3, unplaced) 0.467 7.422 i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q_reg[3] + LUT6 (Prop_lut6_I5_O) 0.124 7.546 r i_ariane/i_cva6/csr_regfile_i/FSM_sequential_state_q[3]_i_9/O + net (fo=13, unplaced) 0.499 8.045 i_ariane/i_cva6/issue_stage_i/i_scoreboard/set_debug_pc + LUT5 (Prop_lut5_I3_O) 0.124 8.169 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/FSM_sequential_state_q[3]_i_2/O + net (fo=151, unplaced) 0.559 8.728 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/flush_ctrl_id + LUT6 (Prop_lut6_I0_O) 0.124 8.852 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46/O + net (fo=2, unplaced) 0.460 9.312 i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[0][sbe][rd][4]_i_46_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 9.436 f i_ariane/i_cva6/ex_stage_i/i_mult/i_div/mem_q[1][sbe][result][31]_i_8/O + net (fo=6, unplaced) 0.481 9.917 i_ariane/i_cva6/issue_stage_i/i_scoreboard/flu_trans_id_ex_id[0] + LUT6 (Prop_lut6_I4_O) 0.124 10.041 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39/O + net (fo=2, unplaced) 0.913 10.954 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_39_n_1 + LUT6 (Prop_lut6_I0_O) 0.124 11.078 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22/O + net (fo=1, unplaced) 0.449 11.527 i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_22_n_1 + LUT5 (Prop_lut5_I2_O) 0.124 11.651 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/vaddr_to_be_flushed[15]_i_9/O + net (fo=3, unplaced) 0.467 12.118 i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_16 + LUT6 (Prop_lut6_I0_O) 0.124 12.242 r i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/issue_q[sbe][pc][31]_i_36/O + net (fo=1, unplaced) 0.449 12.691 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_0[0] + LUT6 (Prop_lut6_I2_O) 0.124 12.815 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_q[sbe][pc][31]_i_16/O + net (fo=2, unplaced) 0.460 13.275 i_ariane/i_cva6/issue_stage_i/i_scoreboard/rs1_valid_sb_iro + LUT6 (Prop_lut6_I4_O) 0.124 13.399 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4/O + net (fo=1, unplaced) 0.449 13.848 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 13.972 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2/O + net (fo=30, unplaced) 0.519 14.491 i_ariane/i_cva6/issue_stage_i/i_scoreboard/issue_pointer_q[1]_i_2_n_1 + LUT5 (Prop_lut5_I0_O) 0.124 14.615 r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2/O + net (fo=4, unplaced) 0.926 15.541 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[3][sbe][fu][0]_i_2_n_1 + LUT5 (Prop_lut5_I2_O) 0.148 15.689 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14/O + net (fo=4, unplaced) 0.926 16.615 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_14_n_1 + LUT6 (Prop_lut6_I1_O) 0.124 16.739 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4/O + net (fo=6, unplaced) 0.934 17.673 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_4_n_1 + LUT6 (Prop_lut6_I2_O) 0.124 17.797 f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1/O + net (fo=5, unplaced) 0.501 18.298 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q[0][sbe][rd][4]_i_1_n_1 + FDCE f i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/CE + ------------------------------------------------------------------- ------------------- + + (clock clk_out1_xlnx_clk_gen rise edge) + 20.000 20.000 r + K17 0.000 20.000 r clk_sys (IN) + net (fo=0) 0.000 20.000 i_xlnx_clk_gen/inst/clk_in1 + K17 IBUF (Prop_ibuf_I_O) 1.404 21.404 r i_xlnx_clk_gen/inst/clkin1_ibufg/O + net (fo=1, unplaced) 0.439 21.843 i_xlnx_clk_gen/inst/clk_in1_xlnx_clk_gen + MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) + -5.378 16.466 r i_xlnx_clk_gen/inst/mmcm_adv_inst/CLKOUT0 + net (fo=1, unplaced) 0.760 17.225 i_xlnx_clk_gen/inst/clk_out1_xlnx_clk_gen + BUFG (Prop_bufg_I_O) 0.091 17.316 r i_xlnx_clk_gen/inst/clkout1_buf/O + net (fo=21611, unplaced) 0.439 17.755 i_ariane/i_cva6/issue_stage_i/i_scoreboard/clk_out1 + FDCE r i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0]/C + clock pessimism 0.531 18.286 + clock uncertainty -0.079 18.206 + FDCE (Setup_fdce_C_CE) -0.202 18.004 i_ariane/i_cva6/issue_stage_i/i_scoreboard/mem_q_reg[0][sbe][rd][0] + ------------------------------------------------------------------- + required time 18.004 + arrival time -18.298 + ------------------------------------------------------------------- + slack -0.293 + + + + diff --git a/REPORT/reports_cva6_fpga_synth/cva6_fpga.utilization.rpt b/REPORT/reports_cva6_fpga_synth/cva6_fpga.utilization.rpt new file mode 100644 index 00000000..d6935392 --- /dev/null +++ b/REPORT/reports_cva6_fpga_synth/cva6_fpga.utilization.rpt @@ -0,0 +1,847 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 +| Date : Mon Apr 29 18:24:00 2024 +| Host : rootmin-Nitro-AN515-57 running 64-bit Ubuntu 22.04.4 LTS +| Command : report_utilization -hierarchical -file reports_cva6_fpga_synth/cva6_fpga.utilization.rpt +| Design : cva6_zybo_z7_20 +| Device : xc7z020clg400-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Utilization by Hierarchy + +1. Utilization by Hierarchy +--------------------------- + ++-----------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | ++-----------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ +| cva6_zybo_z7_20 | (top) | 37106 | 36201 | 840 | 65 | 20086 | 66 | 1 | 4 | +| (cva6_zybo_z7_20) | (top) | 519 | 37 | 482 | 0 | 3 | 0 | 0 | 0 | +| i_ariane | ariane | 24701 | 24423 | 278 | 0 | 9854 | 16 | 1 | 4 | +| gen_example_coprocessor.i_cvxif_coprocessor | cvxif_example_coprocessor | 15077 | 15027 | 50 | 0 | 5169 | 0 | 0 | 0 | +| (gen_example_coprocessor.i_cvxif_coprocessor) | cvxif_example_coprocessor | 2300 | 2300 | 0 | 0 | 2720 | 0 | 0 | 0 | +| fifo_commit_i | fifo_v3__parameterized6 | 171 | 121 | 50 | 0 | 10 | 0 | 0 | 0 | +| (fifo_commit_i) | fifo_v3__parameterized6 | 42 | 42 | 0 | 0 | 10 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized6 | 129 | 79 | 50 | 0 | 0 | 0 | 0 | 0 | +| inputs_registers | cvxif_registers__parameterized0 | 5182 | 5182 | 0 | 0 | 1220 | 0 | 0 | 0 | +| weights_registers | cvxif_registers | 7730 | 7730 | 0 | 0 | 1219 | 0 | 0 | 0 | +| i_cva6 | cva6 | 9624 | 9396 | 228 | 0 | 4685 | 16 | 1 | 4 | +| (i_cva6) | cva6 | 60 | 0 | 60 | 0 | 0 | 0 | 0 | 0 | +| csr_regfile_i | csr_regfile | 287 | 287 | 0 | 0 | 706 | 0 | 0 | 0 | +| ex_stage_i | ex_stage | 2600 | 2600 | 0 | 0 | 1815 | 4 | 0 | 4 | +| (ex_stage_i) | ex_stage | 0 | 0 | 0 | 0 | 34 | 0 | 0 | 0 | +| csr_buffer_i | csr_buffer | 622 | 622 | 0 | 0 | 13 | 0 | 0 | 0 | +| gen_cvxif.cvxif_fu_i | cvxif_fu | 1 | 1 | 0 | 0 | 35 | 0 | 0 | 0 | +| i_mult | mult | 301 | 301 | 0 | 0 | 155 | 0 | 0 | 4 | +| i_div | serdiv | 202 | 202 | 0 | 0 | 111 | 0 | 0 | 0 | +| i_multiplier | multiplier | 99 | 99 | 0 | 0 | 44 | 0 | 0 | 4 | +| lsu_i | load_store_unit | 1676 | 1676 | 0 | 0 | 1578 | 4 | 0 | 0 | +| gen_mmu_sv32.i_cva6_mmu | cva6_mmu_sv32 | 838 | 838 | 0 | 0 | 589 | 4 | 0 | 0 | +| (gen_mmu_sv32.i_cva6_mmu) | cva6_mmu_sv32 | 25 | 25 | 0 | 0 | 96 | 0 | 0 | 0 | +| i_dtlb | cva6_tlb_sv32 | 95 | 95 | 0 | 0 | 99 | 0 | 0 | 0 | +| i_itlb | cva6_tlb_sv32_335 | 99 | 99 | 0 | 0 | 95 | 0 | 0 | 0 | +| i_ptw | cva6_ptw_sv32 | 373 | 373 | 0 | 0 | 105 | 0 | 0 | 0 | +| i_shared_tlb | cva6_shared_tlb_sv32 | 246 | 246 | 0 | 0 | 194 | 4 | 0 | 0 | +| (i_shared_tlb) | cva6_shared_tlb_sv32 | 37 | 37 | 0 | 0 | 186 | 0 | 0 | 0 | +| gen_sram[0].pte_sram | sram__parameterized3 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper__parameterized0_343 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64__parameterized0_344 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[0].tag_sram | sram__parameterized2 | 30 | 30 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper__parameterized0_341 | 30 | 30 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64__parameterized0_342 | 30 | 30 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[1].pte_sram | sram__parameterized3_336 | 26 | 26 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper__parameterized0_339 | 26 | 26 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64__parameterized0_340 | 26 | 26 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[1].tag_sram | sram__parameterized2_337 | 39 | 39 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64__parameterized0 | 39 | 39 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_lfsr | lfsr_338 | 114 | 114 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_load_unit | load_unit | 77 | 77 | 0 | 0 | 63 | 0 | 0 | 0 | +| i_pipe_reg_load | shift_reg | 184 | 184 | 0 | 0 | 72 | 0 | 0 | 0 | +| i_store_unit | store_unit | 334 | 334 | 0 | 0 | 686 | 0 | 0 | 0 | +| (i_store_unit) | store_unit | 10 | 10 | 0 | 0 | 46 | 0 | 0 | 0 | +| i_amo_buffer | amo_buffer | 67 | 67 | 0 | 0 | 74 | 0 | 0 | 0 | +| i_amo_fifo | fifo_v3__parameterized13 | 67 | 67 | 0 | 0 | 74 | 0 | 0 | 0 | +| (i_amo_fifo) | fifo_v3__parameterized13 | 27 | 27 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized13 | 40 | 40 | 0 | 0 | 72 | 0 | 0 | 0 | +| store_buffer_i | store_buffer | 257 | 257 | 0 | 0 | 566 | 0 | 0 | 0 | +| lsu_bypass_i | lsu_bypass | 243 | 243 | 0 | 0 | 168 | 0 | 0 | 0 | +| gen_cache_wt.i_cache_subsystem | wt_cache_subsystem | 2418 | 2322 | 96 | 0 | 857 | 12 | 0 | 0 | +| (gen_cache_wt.i_cache_subsystem) | wt_cache_subsystem | 291 | 287 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_adapter | wt_axi_adapter | 738 | 646 | 92 | 0 | 315 | 0 | 0 | 0 | +| (i_adapter) | wt_axi_adapter | 143 | 143 | 0 | 0 | 277 | 0 | 0 | 0 | +| i_axi_shim | axi_shim | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_b_fifo | fifo_v3__parameterized10 | 31 | 27 | 4 | 0 | 7 | 0 | 0 | 0 | +| (i_b_fifo) | fifo_v3__parameterized10 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized10 | 22 | 18 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_dcache_data_fifo | fifo_v3__parameterized9 | 498 | 442 | 56 | 0 | 4 | 0 | 0 | 0 | +| (i_dcache_data_fifo) | fifo_v3__parameterized9 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized9 | 496 | 440 | 56 | 0 | 0 | 0 | 0 | 0 | +| i_icache_data_fifo | fifo_v3__parameterized8 | 24 | 0 | 24 | 0 | 4 | 0 | 0 | 0 | +| (i_icache_data_fifo) | fifo_v3__parameterized8 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized8 | 24 | 0 | 24 | 0 | 0 | 0 | 0 | 0 | +| i_rd_dcache_id | fifo_v3__parameterized7_331 | 11 | 7 | 4 | 0 | 7 | 0 | 0 | 0 | +| (i_rd_dcache_id) | fifo_v3__parameterized7_331 | 4 | 4 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized7_334 | 7 | 3 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_rd_icache_id | fifo_v3__parameterized7_332 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | +| i_rr_arb_tree | rr_arb_tree__parameterized7 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_wr_dcache_id | fifo_v3__parameterized7_333 | 16 | 12 | 4 | 0 | 7 | 0 | 0 | 0 | +| (i_wr_dcache_id) | fifo_v3__parameterized7_333 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized7 | 8 | 4 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_cva6_icache | cva6_icache | 177 | 177 | 0 | 0 | 80 | 6 | 0 | 0 | +| (i_cva6_icache) | cva6_icache | 20 | 20 | 0 | 0 | 72 | 0 | 0 | 0 | +| gen_sram[0].data_sram | sram__parameterized0 | 34 | 34 | 0 | 0 | 0 | 2 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_327 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_330 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[1].i_tc_sram_wrapper | tc_sram_wrapper_328 | 34 | 34 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_329 | 34 | 34 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[0].tag_sram | sram_315 | 43 | 43 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_325 | 43 | 43 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_326 | 43 | 43 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[1].data_sram | sram__parameterized0_316 | 49 | 49 | 0 | 0 | 0 | 2 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_321 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_324 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[1].i_tc_sram_wrapper | tc_sram_wrapper_322 | 49 | 49 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_323 | 49 | 49 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_sram[1].tag_sram | sram_317 | 28 | 28 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_319 | 28 | 28 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_320 | 28 | 28 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_lfsr | lfsr_318 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_wt_dcache | wt_dcache | 1212 | 1212 | 0 | 0 | 462 | 6 | 0 | 0 | +| gen_rd_ports[0].i_wt_dcache_ctrl | wt_dcache_ctrl | 56 | 56 | 0 | 0 | 40 | 0 | 0 | 0 | +| gen_rd_ports[1].i_wt_dcache_ctrl | wt_dcache_ctrl_299 | 54 | 54 | 0 | 0 | 44 | 0 | 0 | 0 | +| gen_rd_ports[2].i_wt_dcache_ctrl | wt_dcache_ctrl_300 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | +| i_wt_dcache_mem | wt_dcache_mem | 151 | 151 | 0 | 0 | 15 | 6 | 0 | 0 | +| (i_wt_dcache_mem) | wt_dcache_mem | 11 | 11 | 0 | 0 | 13 | 0 | 0 | 0 | +| gen_data_banks[0].i_data_sram | sram__parameterized1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_313 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_314 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_data_banks[1].i_data_sram | sram__parameterized1_301 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_311 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_312 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_data_banks[2].i_data_sram | sram__parameterized1_302 | 50 | 50 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_309 | 50 | 50 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_310 | 50 | 50 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_data_banks[3].i_data_sram | sram__parameterized1_303 | 38 | 38 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_307 | 38 | 38 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_308 | 38 | 38 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_tag_srams[0].i_tag_sram | sram | 10 | 10 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper_305 | 10 | 10 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64_306 | 10 | 10 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_tag_srams[1].i_tag_sram | sram_304 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| gen_cut[0].i_tc_sram_wrapper | tc_sram_wrapper | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_ram | SyncSpRamBeNx64 | 8 | 8 | 0 | 0 | 0 | 1 | 0 | 0 | +| i_rr_arb_tree | rr_arb_tree__parameterized6 | 26 | 26 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_wt_dcache_missunit | wt_dcache_missunit | 245 | 245 | 0 | 0 | 118 | 0 | 0 | 0 | +| (i_wt_dcache_missunit) | wt_dcache_missunit | 128 | 128 | 0 | 0 | 62 | 0 | 0 | 0 | +| i_exp_backoff | exp_backoff | 28 | 28 | 0 | 0 | 48 | 0 | 0 | 0 | +| i_lfsr_inv | lfsr | 89 | 89 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_wt_dcache_wbuffer | wt_dcache_wbuffer | 699 | 699 | 0 | 0 | 238 | 0 | 0 | 0 | +| (i_wt_dcache_wbuffer) | wt_dcache_wbuffer | 491 | 491 | 0 | 0 | 219 | 0 | 0 | 0 | +| i_clean_rr | rr_arb_tree__parameterized5 | 44 | 44 | 0 | 0 | 1 | 0 | 0 | 0 | +| i_dirty_rr | rr_arb_tree__parameterized4 | 112 | 112 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_rtrn_id_fifo | fifo_v3__parameterized7 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | +| i_tx_id_rr | rr_arb_tree__parameterized3 | 16 | 16 | 0 | 0 | 7 | 0 | 0 | 0 | +| i_frontend | frontend | 540 | 516 | 24 | 0 | 299 | 0 | 1 | 0 | +| (i_frontend) | frontend | 1 | 1 | 0 | 0 | 136 | 0 | 0 | 0 | +| btb_gen.i_btb | btb | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| gen_fpga_btb.gen_btb_ram[0].i_btb_ram | SyncDpRam | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| i_instr_queue | instr_queue | 161 | 137 | 24 | 0 | 47 | 0 | 0 | 0 | +| (i_instr_queue) | instr_queue | 3 | 3 | 0 | 0 | 33 | 0 | 0 | 0 | +| gen_instr_fifo[0].i_fifo_instr_data | fifo_v3__parameterized11 | 51 | 51 | 0 | 0 | 7 | 0 | 0 | 0 | +| i_fifo_address | fifo_v3__parameterized12 | 107 | 83 | 24 | 0 | 7 | 0 | 0 | 0 | +| (i_fifo_address) | fifo_v3__parameterized12 | 15 | 15 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized12 | 92 | 68 | 24 | 0 | 0 | 0 | 0 | 0 | +| i_instr_realign | instr_realign | 361 | 361 | 0 | 0 | 50 | 0 | 0 | 0 | +| ras_gen.i_ras | ras | 17 | 17 | 0 | 0 | 66 | 0 | 0 | 0 | +| id_stage_i | id_stage | 238 | 238 | 0 | 0 | 168 | 0 | 0 | 0 | +| issue_stage_i | issue_stage | 3481 | 3433 | 48 | 0 | 840 | 0 | 0 | 0 | +| i_issue_read_operands | issue_read_operands | 1698 | 1650 | 48 | 0 | 218 | 0 | 0 | 0 | +| (i_issue_read_operands) | issue_read_operands | 1650 | 1650 | 0 | 0 | 218 | 0 | 0 | 0 | +| gen_fpga_regfile.i_ariane_regfile_fpga | ariane_regfile_fpga | 48 | 0 | 48 | 0 | 0 | 0 | 0 | 0 | +| i_scoreboard | scoreboard | 1783 | 1783 | 0 | 0 | 622 | 0 | 0 | 0 | +| i_ariane_peripherals | ariane_peripherals | 2319 | 2319 | 0 | 0 | 2426 | 0 | 0 | 0 | +| gen_timer.i_axi2apb_64_32_timer | axi2apb_64_32 | 304 | 304 | 0 | 0 | 112 | 0 | 0 | 0 | +| (gen_timer.i_axi2apb_64_32_timer) | axi2apb_64_32 | 16 | 16 | 0 | 0 | 92 | 0 | 0 | 0 | +| slave_ar_buffer_i | axi_ar_buffer_274 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_295 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_296 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_297 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_298 | 165 | 165 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_aw_buffer_i | axi_aw_buffer_275 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_291 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_292 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_293 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_294 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_b_buffer_i | axi_b_buffer_276 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized2_287 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized2_288 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized4_289 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized17_290 | 19 | 19 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_r_buffer_i | axi_r_buffer_277 | 78 | 78 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized1_283 | 78 | 78 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized1_284 | 78 | 78 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized3_285 | 78 | 78 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized16_286 | 78 | 78 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_w_buffer_i | axi_w_buffer_278 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized0_279 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized0_280 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized2_281 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized15_282 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_timer.i_timer | apb_timer | 267 | 267 | 0 | 0 | 256 | 0 | 0 | 0 | +| TIMER_GEN[0].timer_i | timer | 124 | 124 | 0 | 0 | 128 | 0 | 0 | 0 | +| TIMER_GEN[1].timer_i | timer_273 | 143 | 143 | 0 | 0 | 128 | 0 | 0 | 0 | +| gen_uart.i_apb_uart | apb_uart | 769 | 769 | 0 | 0 | 1477 | 0 | 0 | 0 | +| (gen_uart.i_apb_uart) | apb_uart | 17 | 17 | 0 | 0 | 102 | 0 | 0 | 0 | +| UART_BG16 | uart_baudgen | 15 | 15 | 0 | 0 | 17 | 0 | 0 | 0 | +| UART_BG2 | slib_clock_div | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| UART_BIDET | slib_edge_detect | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_ED_CTS | slib_edge_detect_262 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_ED_DCD | slib_edge_detect_263 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_ED_DSR | slib_edge_detect_264 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_ED_RI | slib_edge_detect_265 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_FEDET | slib_edge_detect_266 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_IF_CTS | slib_input_filter | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | +| UART_IF_DCD | slib_input_filter_267 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| UART_IF_DSR | slib_input_filter_268 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | +| UART_IF_RI | slib_input_filter_269 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | +| UART_IIC | uart_interrupt | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | +| UART_IIC_THRE_ED | slib_edge_detect_270 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_IS_SIN | slib_input_sync | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| UART_PEDET | slib_edge_detect_271 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_RCLK | slib_edge_detect_272 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| UART_RX | uart_receiver | 49 | 49 | 0 | 0 | 35 | 0 | 0 | 0 | +| (UART_RX) | uart_receiver | 13 | 13 | 0 | 0 | 21 | 0 | 0 | 0 | +| RX_BRC | slib_counter | 13 | 13 | 0 | 0 | 5 | 0 | 0 | 0 | +| RX_IFSB | slib_input_filter__parameterized2 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | +| RX_MVF | slib_mv_filter | 15 | 15 | 0 | 0 | 5 | 0 | 0 | 0 | +| UART_RXFF | slib_fifo__parameterized1 | 367 | 367 | 0 | 0 | 736 | 0 | 0 | 0 | +| UART_TX | uart_transmitter | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | +| UART_TXFF | slib_fifo | 278 | 278 | 0 | 0 | 540 | 0 | 0 | 0 | +| i_axi2apb_64_32_plic | axi2apb_64_32_230 | 545 | 545 | 0 | 0 | 164 | 0 | 0 | 0 | +| (i_axi2apb_64_32_plic) | axi2apb_64_32_230 | 80 | 80 | 0 | 0 | 144 | 0 | 0 | 0 | +| slave_ar_buffer_i | axi_ar_buffer_237 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_258 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_259 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_260 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_261 | 75 | 75 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_aw_buffer_i | axi_aw_buffer_238 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_254 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_255 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_256 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_257 | 254 | 254 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_b_buffer_i | axi_b_buffer_239 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized2_250 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized2_251 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized4_252 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized17_253 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_r_buffer_i | axi_r_buffer_240 | 95 | 95 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized1_246 | 95 | 95 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized1_247 | 95 | 95 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized3_248 | 95 | 95 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized16_249 | 95 | 95 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_w_buffer_i | axi_w_buffer_241 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized0_242 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized0_243 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized2_244 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized15_245 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi2apb_64_32_uart | axi2apb_64_32_231 | 157 | 157 | 0 | 0 | 64 | 0 | 0 | 0 | +| (i_axi2apb_64_32_uart) | axi2apb_64_32_231 | 15 | 15 | 0 | 0 | 44 | 0 | 0 | 0 | +| slave_ar_buffer_i | axi_ar_buffer | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice_233 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo_234 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1_235 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14_236 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_aw_buffer_i | axi_aw_buffer | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized1 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized14 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_b_buffer_i | axi_b_buffer | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized2 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized2 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized4 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized17 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_r_buffer_i | axi_r_buffer | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized1 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized1 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized3 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized16 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | +| slave_w_buffer_i | axi_w_buffer | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_axi_single_slice | axi_single_slice__parameterized0 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo | fifo__parameterized0 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| impl | fifo_v2__parameterized2 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized15 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_plic | plic_top | 277 | 277 | 0 | 0 | 353 | 0 | 0 | 0 | +| (i_plic) | plic_top | 147 | 147 | 0 | 0 | 282 | 0 | 0 | 0 | +| gen_target[0].i_target | rv_plic_target | 31 | 31 | 0 | 0 | 14 | 0 | 0 | 0 | +| gen_target[1].i_target | rv_plic_target_232 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_rv_plic_gateway | rv_plic_gateway | 88 | 88 | 0 | 0 | 53 | 0 | 0 | 0 | +| i_axi2rom | axi2mem__parameterized0 | 212 | 212 | 0 | 0 | 81 | 0 | 0 | 0 | +| i_axi_dwidth_converter_dm_master | xlnx_axi_dwidth_converter_dm_master | 494 | 430 | 0 | 64 | 617 | 0 | 0 | 0 | +| (i_axi_dwidth_converter_dm_master) | xlnx_axi_dwidth_converter_dm_master | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_top | 494 | 430 | 0 | 64 | 617 | 0 | 0 | 0 | +| gen_upsizer.gen_full_upsizer.axi_upsizer_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_axi_upsizer | 494 | 430 | 0 | 64 | 617 | 0 | 0 | 0 | +| USE_READ.gen_non_fifo_r_upsizer.mi_register_slice_inst | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axi_register_slice | 36 | 36 | 0 | 0 | 136 | 0 | 0 | 0 | +| r.r_pipe | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axic_register_slice__parameterized2 | 36 | 36 | 0 | 0 | 136 | 0 | 0 | 0 | +| USE_READ.gen_non_fifo_r_upsizer.read_data_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_r_upsizer | 58 | 58 | 0 | 0 | 84 | 0 | 0 | 0 | +| USE_READ.read_addr_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_a_upsizer__parameterized0 | 69 | 37 | 0 | 32 | 49 | 0 | 0 | 0 | +| (USE_READ.read_addr_inst) | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_a_upsizer__parameterized0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| GEN_CMD_QUEUE.cmd_queue | xlnx_axi_dwidth_converter_dm_master_generic_baseblocks_v2_1_1_command_fifo__parameterized0_1 | 55 | 27 | 0 | 28 | 36 | 0 | 0 | 0 | +| gen_id_queue.id_queue | xlnx_axi_dwidth_converter_dm_master_generic_baseblocks_v2_1_1_command_fifo_2 | 14 | 10 | 0 | 4 | 12 | 0 | 0 | 0 | +| USE_WRITE.gen_non_fifo_w_upsizer.write_data_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_w_upsizer | 34 | 34 | 0 | 0 | 163 | 0 | 0 | 0 | +| USE_WRITE.write_addr_inst | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_a_upsizer | 171 | 139 | 0 | 32 | 49 | 0 | 0 | 0 | +| (USE_WRITE.write_addr_inst) | xlnx_axi_dwidth_converter_dm_master_axi_dwidth_converter_v2_1_29_a_upsizer | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| GEN_CMD_QUEUE.cmd_queue | xlnx_axi_dwidth_converter_dm_master_generic_baseblocks_v2_1_1_command_fifo__parameterized0 | 154 | 126 | 0 | 28 | 36 | 0 | 0 | 0 | +| gen_id_queue.id_queue | xlnx_axi_dwidth_converter_dm_master_generic_baseblocks_v2_1_1_command_fifo | 17 | 13 | 0 | 4 | 12 | 0 | 0 | 0 | +| si_register_slice_inst | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axi_register_slice__parameterized0 | 126 | 126 | 0 | 0 | 136 | 0 | 0 | 0 | +| ar.ar_pipe | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axic_register_slice__parameterized3 | 60 | 60 | 0 | 0 | 68 | 0 | 0 | 0 | +| aw.aw_pipe | xlnx_axi_dwidth_converter_dm_master_axi_register_slice_v2_1_29_axic_register_slice__parameterized3_0 | 66 | 66 | 0 | 0 | 68 | 0 | 0 | 0 | +| i_axi_dwidth_converter_dm_slave | xlnx_axi_dwidth_converter_dm_slave | 775 | 731 | 44 | 0 | 742 | 0 | 0 | 0 | +| (i_axi_dwidth_converter_dm_slave) | xlnx_axi_dwidth_converter_dm_slave | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_top | 775 | 731 | 44 | 0 | 742 | 0 | 0 | 0 | +| gen_downsizer.gen_simple_downsizer.axi_downsizer_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_axi_downsizer | 775 | 731 | 44 | 0 | 742 | 0 | 0 | 0 | +| USE_READ.read_addr_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_a_downsizer__parameterized0 | 315 | 295 | 20 | 0 | 297 | 0 | 0 | 0 | +| (USE_READ.read_addr_inst) | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_a_downsizer__parameterized0 | 188 | 188 | 0 | 0 | 209 | 0 | 0 | 0 | +| cmd_queue | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_axic_fifo__parameterized0 | 127 | 107 | 20 | 0 | 88 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen__parameterized0 | 127 | 107 | 20 | 0 | 88 | 0 | 0 | 0 | +| (inst) | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen__parameterized0 | 72 | 72 | 0 | 0 | 0 | 0 | 0 | 0 | +| fifo_gen_inst | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9__parameterized0 | 55 | 35 | 20 | 0 | 88 | 0 | 0 | 0 | +| (fifo_gen_inst) | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst_fifo_gen | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9_synth__parameterized0 | 55 | 35 | 20 | 0 | 88 | 0 | 0 | 0 | +| gconvfifo.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_top__parameterized0 | 55 | 35 | 20 | 0 | 88 | 0 | 0 | 0 | +| grf.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_ramfifo__parameterized0 | 55 | 35 | 20 | 0 | 88 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | xlnx_axi_dwidth_converter_dm_slave_rd_logic_7 | 10 | 10 | 0 | 0 | 20 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | xlnx_axi_dwidth_converter_dm_slave_rd_fwft_13 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| grss.rsts | xlnx_axi_dwidth_converter_dm_slave_rd_status_flags_ss_14 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | xlnx_axi_dwidth_converter_dm_slave_rd_bin_cntr_15 | 3 | 3 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | xlnx_axi_dwidth_converter_dm_slave_wr_logic_8 | 14 | 14 | 0 | 0 | 12 | 0 | 0 | 0 | +| gwss.wsts | xlnx_axi_dwidth_converter_dm_slave_wr_status_flags_ss_11 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | xlnx_axi_dwidth_converter_dm_slave_wr_bin_cntr_12 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | xlnx_axi_dwidth_converter_dm_slave_memory__parameterized0_9 | 20 | 0 | 20 | 0 | 52 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | xlnx_axi_dwidth_converter_dm_slave_memory__parameterized0_9 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | +| gdm.dm_gen.dm | xlnx_axi_dwidth_converter_dm_slave_dmem__parameterized0_10 | 20 | 0 | 20 | 0 | 26 | 0 | 0 | 0 | +| rstblk | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| (rstblk) | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo | 11 | 11 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | xlnx_axi_dwidth_converter_dm_slave_xpm_cdc_async_rst | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| USE_READ.read_data_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_r_downsizer | 51 | 51 | 0 | 0 | 78 | 0 | 0 | 0 | +| USE_WRITE.USE_SPLIT.write_resp_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_b_downsizer | 17 | 17 | 0 | 0 | 11 | 0 | 0 | 0 | +| USE_WRITE.write_addr_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_a_downsizer | 356 | 332 | 24 | 0 | 344 | 0 | 0 | 0 | +| (USE_WRITE.write_addr_inst) | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_a_downsizer | 191 | 191 | 0 | 0 | 212 | 0 | 0 | 0 | +| USE_B_CHANNEL.cmd_b_queue | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_axic_fifo | 53 | 49 | 4 | 0 | 46 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen | 53 | 49 | 4 | 0 | 46 | 0 | 0 | 0 | +| (inst) | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen | 14 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | +| fifo_gen_inst | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9 | 39 | 35 | 4 | 0 | 46 | 0 | 0 | 0 | +| (fifo_gen_inst) | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst_fifo_gen | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9_synth | 39 | 35 | 4 | 0 | 46 | 0 | 0 | 0 | +| gconvfifo.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_top | 39 | 35 | 4 | 0 | 46 | 0 | 0 | 0 | +| grf.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_ramfifo | 39 | 35 | 4 | 0 | 46 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | xlnx_axi_dwidth_converter_dm_slave_rd_logic_0 | 10 | 10 | 0 | 0 | 20 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | xlnx_axi_dwidth_converter_dm_slave_rd_fwft_4 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| grss.rsts | xlnx_axi_dwidth_converter_dm_slave_rd_status_flags_ss_5 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | xlnx_axi_dwidth_converter_dm_slave_rd_bin_cntr_6 | 3 | 3 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | xlnx_axi_dwidth_converter_dm_slave_wr_logic_1 | 14 | 14 | 0 | 0 | 12 | 0 | 0 | 0 | +| gwss.wsts | xlnx_axi_dwidth_converter_dm_slave_wr_status_flags_ss_2 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | xlnx_axi_dwidth_converter_dm_slave_wr_bin_cntr_3 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | xlnx_axi_dwidth_converter_dm_slave_memory | 4 | 0 | 4 | 0 | 10 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | xlnx_axi_dwidth_converter_dm_slave_memory | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | +| gdm.dm_gen.dm | xlnx_axi_dwidth_converter_dm_slave_dmem | 4 | 0 | 4 | 0 | 5 | 0 | 0 | 0 | +| rstblk | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo__xdcDup__1 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| (rstblk) | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo__xdcDup__1 | 11 | 11 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | xlnx_axi_dwidth_converter_dm_slave_xpm_cdc_async_rst__3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| cmd_queue | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_axic_fifo__parameterized0__xdcDup__1 | 112 | 92 | 20 | 0 | 86 | 0 | 0 | 0 | +| inst | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen__parameterized0__xdcDup__1 | 112 | 92 | 20 | 0 | 86 | 0 | 0 | 0 | +| (inst) | xlnx_axi_dwidth_converter_dm_slave_axi_data_fifo_v2_1_28_fifo_gen__parameterized0__xdcDup__1 | 57 | 57 | 0 | 0 | 0 | 0 | 0 | 0 | +| fifo_gen_inst | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9__parameterized0__xdcDup__1 | 55 | 35 | 20 | 0 | 86 | 0 | 0 | 0 | +| (fifo_gen_inst) | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9__parameterized0__xdcDup__1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst_fifo_gen | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_v13_2_9_synth__parameterized0__xdcDup__1 | 55 | 35 | 20 | 0 | 86 | 0 | 0 | 0 | +| gconvfifo.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_top__parameterized0__xdcDup__1 | 55 | 35 | 20 | 0 | 86 | 0 | 0 | 0 | +| grf.rf | xlnx_axi_dwidth_converter_dm_slave_fifo_generator_ramfifo__parameterized0__xdcDup__1 | 55 | 35 | 20 | 0 | 86 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.rd | xlnx_axi_dwidth_converter_dm_slave_rd_logic | 10 | 10 | 0 | 0 | 20 | 0 | 0 | 0 | +| gr1.gr1_int.rfwft | xlnx_axi_dwidth_converter_dm_slave_rd_fwft | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | +| grss.rsts | xlnx_axi_dwidth_converter_dm_slave_rd_status_flags_ss | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| rpntr | xlnx_axi_dwidth_converter_dm_slave_rd_bin_cntr | 3 | 3 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.gl0.wr | xlnx_axi_dwidth_converter_dm_slave_wr_logic | 14 | 14 | 0 | 0 | 12 | 0 | 0 | 0 | +| gwss.wsts | xlnx_axi_dwidth_converter_dm_slave_wr_status_flags_ss | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| wpntr | xlnx_axi_dwidth_converter_dm_slave_wr_bin_cntr | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| gntv_or_sync_fifo.mem | xlnx_axi_dwidth_converter_dm_slave_memory__parameterized0 | 20 | 0 | 20 | 0 | 50 | 0 | 0 | 0 | +| (gntv_or_sync_fifo.mem) | xlnx_axi_dwidth_converter_dm_slave_memory__parameterized0 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | +| gdm.dm_gen.dm | xlnx_axi_dwidth_converter_dm_slave_dmem__parameterized0 | 20 | 0 | 20 | 0 | 25 | 0 | 0 | 0 | +| rstblk | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo__xdcDup__2 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | +| (rstblk) | xlnx_axi_dwidth_converter_dm_slave_reset_blk_ramfifo__xdcDup__2 | 11 | 11 | 0 | 0 | 2 | 0 | 0 | 0 | +| ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst | xlnx_axi_dwidth_converter_dm_slave_xpm_cdc_async_rst__4 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| USE_WRITE.write_data_inst | xlnx_axi_dwidth_converter_dm_slave_axi_dwidth_converter_v2_1_29_w_downsizer | 36 | 36 | 0 | 0 | 12 | 0 | 0 | 0 | +| i_axi_riscv_atomics | axi_riscv_atomics_wrap | 1385 | 1385 | 0 | 0 | 593 | 0 | 0 | 0 | +| i_atomics | axi_riscv_atomics | 1385 | 1385 | 0 | 0 | 593 | 0 | 0 | 0 | +| i_amos | axi_riscv_amos | 1131 | 1131 | 0 | 0 | 277 | 0 | 0 | 0 | +| i_lrsc | axi_riscv_lrsc | 254 | 254 | 0 | 0 | 316 | 0 | 0 | 0 | +| (i_lrsc) | axi_riscv_lrsc | 29 | 29 | 0 | 0 | 44 | 0 | 0 | 0 | +| i_art | axi_res_tbl | 225 | 225 | 0 | 0 | 272 | 0 | 0 | 0 | +| i_axi_xbar | axi_xbar_intf | 5020 | 4988 | 32 | 0 | 4417 | 0 | 0 | 0 | +| i_xbar | axi_xbar | 5020 | 4988 | 32 | 0 | 4417 | 0 | 0 | 0 | +| (i_xbar) | axi_xbar | 11 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_mst_port_mux[0].i_axi_mux | axi_mux | 362 | 362 | 0 | 0 | 540 | 0 | 0 | 0 | +| (gen_mst_port_mux[0].i_axi_mux) | axi_mux | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_216 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_217 | 38 | 38 | 0 | 0 | 104 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_229 | 38 | 38 | 0 | 0 | 104 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_218 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_219 | 151 | 151 | 0 | 0 | 114 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_228 | 151 | 151 | 0 | 0 | 114 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_220 | 18 | 18 | 0 | 0 | 16 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_227 | 18 | 18 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_221 | 103 | 103 | 0 | 0 | 146 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_226 | 103 | 103 | 0 | 0 | 146 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_222 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_222 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_225 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_223 | 40 | 40 | 0 | 0 | 148 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_224 | 40 | 40 | 0 | 0 | 148 | 0 | 0 | 0 | +| gen_mst_port_mux[1].i_axi_mux | axi_mux_0 | 100 | 100 | 0 | 0 | 22 | 0 | 0 | 0 | +| (gen_mst_port_mux[1].i_axi_mux) | axi_mux_0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_202 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_203 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_215 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_204 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_205 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_214 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_206 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_213 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_207 | 73 | 73 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_212 | 73 | 73 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_208 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_208 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_211 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_209 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_210 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_mst_port_mux[2].i_axi_mux | axi_mux_1 | 45 | 45 | 0 | 0 | 27 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_190 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_191 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_201 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_192 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_193 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_200 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_194 | 15 | 15 | 0 | 0 | 10 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_199 | 15 | 15 | 0 | 0 | 10 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_195 | 17 | 17 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_198 | 17 | 17 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_196 | 10 | 10 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_196 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_197 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mst_port_mux[3].i_axi_mux | axi_mux_2 | 34 | 34 | 0 | 0 | 27 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_178 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_179 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_189 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_180 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_181 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_188 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_182 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_187 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_183 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_186 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_184 | 11 | 11 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_184 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_185 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mst_port_mux[4].i_axi_mux | axi_mux_3 | 328 | 328 | 0 | 0 | 402 | 0 | 0 | 0 | +| (gen_mst_port_mux[4].i_axi_mux) | axi_mux_3 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_164 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_165 | 25 | 25 | 0 | 0 | 42 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_177 | 25 | 25 | 0 | 0 | 42 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_166 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_167 | 22 | 22 | 0 | 0 | 42 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_176 | 22 | 22 | 0 | 0 | 42 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_168 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_175 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_169 | 172 | 172 | 0 | 0 | 146 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_174 | 172 | 172 | 0 | 0 | 146 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_170 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_170 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_173 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_171 | 75 | 75 | 0 | 0 | 148 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_172 | 75 | 75 | 0 | 0 | 148 | 0 | 0 | 0 | +| gen_mst_port_mux[5].i_axi_mux | axi_mux_4 | 127 | 127 | 0 | 0 | 242 | 0 | 0 | 0 | +| (gen_mst_port_mux[5].i_axi_mux) | axi_mux_4 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_150 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_151 | 26 | 26 | 0 | 0 | 42 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_163 | 26 | 26 | 0 | 0 | 42 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_152 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_153 | 23 | 23 | 0 | 0 | 42 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_162 | 23 | 23 | 0 | 0 | 42 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_154 | 6 | 6 | 0 | 0 | 12 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_161 | 6 | 6 | 0 | 0 | 12 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_155 | 18 | 18 | 0 | 0 | 58 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_160 | 18 | 18 | 0 | 0 | 58 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_156 | 10 | 10 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_156 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_159 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_157 | 39 | 39 | 0 | 0 | 76 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_158 | 39 | 39 | 0 | 0 | 76 | 0 | 0 | 0 | +| gen_mst_port_mux[6].i_axi_mux | axi_mux_5 | 287 | 287 | 0 | 0 | 518 | 0 | 0 | 0 | +| (gen_mst_port_mux[6].i_axi_mux) | axi_mux_5 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_136 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_137 | 54 | 54 | 0 | 0 | 100 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_149 | 54 | 54 | 0 | 0 | 100 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_138 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_139 | 52 | 52 | 0 | 0 | 100 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_148 | 52 | 52 | 0 | 0 | 100 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_140 | 13 | 13 | 0 | 0 | 12 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_147 | 13 | 13 | 0 | 0 | 12 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_141 | 81 | 81 | 0 | 0 | 146 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_146 | 81 | 81 | 0 | 0 | 146 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_142 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_142 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_145 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_143 | 75 | 75 | 0 | 0 | 148 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_144 | 75 | 75 | 0 | 0 | 148 | 0 | 0 | 0 | +| gen_mst_port_mux[7].i_axi_mux | axi_mux_6 | 137 | 137 | 0 | 0 | 376 | 0 | 0 | 0 | +| (gen_mst_port_mux[7].i_axi_mux) | axi_mux_6 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_122 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_123 | 19 | 19 | 0 | 0 | 40 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_135 | 19 | 19 | 0 | 0 | 40 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_124 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_125 | 23 | 23 | 0 | 0 | 40 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_134 | 23 | 23 | 0 | 0 | 40 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_126 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_133 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_127 | 38 | 38 | 0 | 0 | 138 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_132 | 38 | 38 | 0 | 0 | 138 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_128 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_128 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_131 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_129 | 38 | 38 | 0 | 0 | 138 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_130 | 38 | 38 | 0 | 0 | 138 | 0 | 0 | 0 | +| gen_mst_port_mux[8].i_axi_mux | axi_mux_7 | 366 | 366 | 0 | 0 | 346 | 0 | 0 | 0 | +| (gen_mst_port_mux[8].i_axi_mux) | axi_mux_7 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2_108 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6_109 | 42 | 42 | 0 | 0 | 92 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6_121 | 42 | 42 | 0 | 0 | 92 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1_110 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4_111 | 51 | 51 | 0 | 0 | 92 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4_120 | 51 | 51 | 0 | 0 | 92 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5_112 | 83 | 83 | 0 | 0 | 8 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5_119 | 83 | 83 | 0 | 0 | 8 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7_113 | 170 | 170 | 0 | 0 | 138 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7_118 | 170 | 170 | 0 | 0 | 138 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4_114 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4_114 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4_117 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_115 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_116 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mst_port_mux[9].i_axi_mux | axi_mux_8 | 184 | 184 | 0 | 0 | 582 | 0 | 0 | 0 | +| (gen_mst_port_mux[9].i_axi_mux) | axi_mux_8 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_ar_arbiter | rr_arb_tree__parameterized2 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_ar_spill_reg | spill_register__parameterized6 | 39 | 39 | 0 | 0 | 130 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized6 | 39 | 39 | 0 | 0 | 130 | 0 | 0 | 0 | +| gen_mux.i_aw_arbiter | rr_arb_tree__parameterized1 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_mux.i_aw_spill_reg | spill_register__parameterized4 | 36 | 36 | 0 | 0 | 130 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized4 | 36 | 36 | 0 | 0 | 130 | 0 | 0 | 0 | +| gen_mux.i_b_spill_reg | spill_register__parameterized5 | 10 | 10 | 0 | 0 | 16 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized5 | 10 | 10 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_mux.i_r_spill_reg | spill_register__parameterized7 | 43 | 43 | 0 | 0 | 146 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized7 | 43 | 43 | 0 | 0 | 146 | 0 | 0 | 0 | +| gen_mux.i_w_fifo | fifo_v3__parameterized4 | 10 | 10 | 0 | 0 | 3 | 0 | 0 | 0 | +| (gen_mux.i_w_fifo) | fifo_v3__parameterized4 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized4 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | +| gen_mux.i_w_spill_reg | spill_register__parameterized0_106 | 41 | 41 | 0 | 0 | 148 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_107 | 41 | 41 | 0 | 0 | 148 | 0 | 0 | 0 | +| gen_slv_port_demux[0].i_axi_ar_decode | addr_decode | 267 | 267 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[0].i_axi_aw_decode | addr_decode_9 | 267 | 267 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[0].i_axi_demux | axi_demux | 719 | 719 | 0 | 0 | 568 | 0 | 0 | 0 | +| (gen_slv_port_demux[0].i_axi_demux) | axi_demux | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.gen_ar_id_counter.i_ar_id_counter | axi_demux_id_counters_58 | 24 | 24 | 0 | 0 | 48 | 0 | 0 | 0 | +| (gen_demux.gen_ar_id_counter.i_ar_id_counter) | axi_demux_id_counters_58 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_counters[0].i_in_flight_cnt | delta_counter_90 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[10].i_in_flight_cnt | delta_counter_91 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[11].i_in_flight_cnt | delta_counter_92 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[12].i_in_flight_cnt | delta_counter_93 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[13].i_in_flight_cnt | delta_counter_94 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[14].i_in_flight_cnt | delta_counter_95 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[15].i_in_flight_cnt | delta_counter_96 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[1].i_in_flight_cnt | delta_counter_97 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[2].i_in_flight_cnt | delta_counter_98 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[3].i_in_flight_cnt | delta_counter_99 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[4].i_in_flight_cnt | delta_counter_100 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[5].i_in_flight_cnt | delta_counter_101 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[6].i_in_flight_cnt | delta_counter_102 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[7].i_in_flight_cnt | delta_counter_103 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[8].i_in_flight_cnt | delta_counter_104 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[9].i_in_flight_cnt | delta_counter_105 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.gen_aw_id_counter.i_aw_id_counter | axi_demux_id_counters_59 | 12 | 12 | 0 | 0 | 48 | 0 | 0 | 0 | +| (gen_demux.gen_aw_id_counter.i_aw_id_counter) | axi_demux_id_counters_59 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_counters[0].i_in_flight_cnt | delta_counter_74 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[10].i_in_flight_cnt | delta_counter_75 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[11].i_in_flight_cnt | delta_counter_76 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[12].i_in_flight_cnt | delta_counter_77 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[13].i_in_flight_cnt | delta_counter_78 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[14].i_in_flight_cnt | delta_counter_79 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[15].i_in_flight_cnt | delta_counter_80 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[1].i_in_flight_cnt | delta_counter_81 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[2].i_in_flight_cnt | delta_counter_82 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[3].i_in_flight_cnt | delta_counter_83 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[4].i_in_flight_cnt | delta_counter_84 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[5].i_in_flight_cnt | delta_counter_85 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[6].i_in_flight_cnt | delta_counter_86 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[7].i_in_flight_cnt | delta_counter_87 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[8].i_in_flight_cnt | delta_counter_88 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[9].i_in_flight_cnt | delta_counter_89 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.i_ar_spill_reg | spill_register__parameterized2_60 | 91 | 91 | 0 | 0 | 90 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized2_73 | 91 | 91 | 0 | 0 | 90 | 0 | 0 | 0 | +| gen_demux.i_aw_spill_reg | spill_register_61 | 247 | 247 | 0 | 0 | 104 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable_72 | 247 | 247 | 0 | 0 | 104 | 0 | 0 | 0 | +| gen_demux.i_b_mux | rr_arb_tree_62 | 33 | 33 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_demux.i_b_spill_reg | spill_register__parameterized1_63 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized1_71 | 8 | 8 | 0 | 0 | 14 | 0 | 0 | 0 | +| gen_demux.i_r_mux | rr_arb_tree__parameterized0_64 | 127 | 127 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_demux.i_r_spill_reg | spill_register__parameterized3_65 | 130 | 130 | 0 | 0 | 140 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized3_70 | 130 | 130 | 0 | 0 | 140 | 0 | 0 | 0 | +| gen_demux.i_w_fifo | fifo_v3_66 | 23 | 23 | 0 | 0 | 6 | 0 | 0 | 0 | +| (gen_demux.i_w_fifo) | fifo_v3_66 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam_69 | 22 | 22 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_demux.i_w_spill_reg | spill_register__parameterized0_67 | 23 | 23 | 0 | 0 | 84 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0_68 | 23 | 23 | 0 | 0 | 84 | 0 | 0 | 0 | +| gen_slv_port_demux[0].i_axi_err_slv | axi_err_slv | 106 | 90 | 16 | 0 | 48 | 0 | 0 | 0 | +| (gen_slv_port_demux[0].i_axi_err_slv) | axi_err_slv | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| i_atop_filter | axi_atop_filter_46 | 50 | 50 | 0 | 0 | 21 | 0 | 0 | 0 | +| (i_atop_filter) | axi_atop_filter_46 | 37 | 37 | 0 | 0 | 19 | 0 | 0 | 0 | +| r_resp_cmd | stream_register_55 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_fifo | fifo_v2_56 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized0_57 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_b_fifo | fifo_v3__parameterized2_47 | 10 | 6 | 4 | 0 | 4 | 0 | 0 | 0 | +| (i_b_fifo) | fifo_v3__parameterized2_47 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized2_54 | 6 | 2 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_r_counter | counter_48 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_counter | delta_counter__parameterized0_53 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_r_fifo | fifo_v3__parameterized3_49 | 15 | 7 | 8 | 0 | 7 | 0 | 0 | 0 | +| (i_r_fifo) | fifo_v3__parameterized3_49 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized3_52 | 9 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | +| i_w_fifo | fifo_v3__parameterized1_50 | 20 | 16 | 4 | 0 | 7 | 0 | 0 | 0 | +| (i_w_fifo) | fifo_v3__parameterized1_50 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized1_51 | 13 | 9 | 4 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[1].i_axi_ar_decode | addr_decode_10 | 252 | 252 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[1].i_axi_aw_decode | addr_decode_11 | 252 | 252 | 0 | 0 | 0 | 0 | 0 | 0 | +| gen_slv_port_demux[1].i_axi_demux | axi_demux_12 | 1150 | 1150 | 0 | 0 | 673 | 0 | 0 | 0 | +| (gen_slv_port_demux[1].i_axi_demux) | axi_demux_12 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.gen_ar_id_counter.i_ar_id_counter | axi_demux_id_counters | 17 | 17 | 0 | 0 | 36 | 0 | 0 | 0 | +| (gen_demux.gen_ar_id_counter.i_ar_id_counter) | axi_demux_id_counters | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_counters[0].i_in_flight_cnt | delta_counter_30 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[10].i_in_flight_cnt | delta_counter_31 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[11].i_in_flight_cnt | delta_counter_32 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[12].i_in_flight_cnt | delta_counter_33 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[13].i_in_flight_cnt | delta_counter_34 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[14].i_in_flight_cnt | delta_counter_35 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[15].i_in_flight_cnt | delta_counter_36 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[1].i_in_flight_cnt | delta_counter_37 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[2].i_in_flight_cnt | delta_counter_38 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[3].i_in_flight_cnt | delta_counter_39 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[4].i_in_flight_cnt | delta_counter_40 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[5].i_in_flight_cnt | delta_counter_41 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[6].i_in_flight_cnt | delta_counter_42 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[7].i_in_flight_cnt | delta_counter_43 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[8].i_in_flight_cnt | delta_counter_44 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[9].i_in_flight_cnt | delta_counter_45 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.gen_aw_id_counter.i_aw_id_counter | axi_demux_id_counters_14 | 17 | 17 | 0 | 0 | 36 | 0 | 0 | 0 | +| (gen_demux.gen_aw_id_counter.i_aw_id_counter) | axi_demux_id_counters_14 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_counters[0].i_in_flight_cnt | delta_counter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[10].i_in_flight_cnt | delta_counter_15 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[11].i_in_flight_cnt | delta_counter_16 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[12].i_in_flight_cnt | delta_counter_17 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[13].i_in_flight_cnt | delta_counter_18 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[14].i_in_flight_cnt | delta_counter_19 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[15].i_in_flight_cnt | delta_counter_20 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[1].i_in_flight_cnt | delta_counter_21 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[2].i_in_flight_cnt | delta_counter_22 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[3].i_in_flight_cnt | delta_counter_23 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[4].i_in_flight_cnt | delta_counter_24 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[5].i_in_flight_cnt | delta_counter_25 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[6].i_in_flight_cnt | delta_counter_26 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[7].i_in_flight_cnt | delta_counter_27 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[8].i_in_flight_cnt | delta_counter_28 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_counters[9].i_in_flight_cnt | delta_counter_29 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_demux.i_ar_spill_reg | spill_register__parameterized2 | 310 | 310 | 0 | 0 | 135 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized2 | 310 | 310 | 0 | 0 | 135 | 0 | 0 | 0 | +| gen_demux.i_aw_spill_reg | spill_register | 153 | 153 | 0 | 0 | 132 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable | 153 | 153 | 0 | 0 | 132 | 0 | 0 | 0 | +| gen_demux.i_b_mux | rr_arb_tree | 34 | 34 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_demux.i_b_spill_reg | spill_register__parameterized1 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized1 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| gen_demux.i_r_mux | rr_arb_tree__parameterized0 | 138 | 138 | 0 | 0 | 16 | 0 | 0 | 0 | +| gen_demux.i_r_spill_reg | spill_register__parameterized3 | 40 | 40 | 0 | 0 | 136 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized3 | 40 | 40 | 0 | 0 | 136 | 0 | 0 | 0 | +| gen_demux.i_w_fifo | fifo_v3 | 23 | 23 | 0 | 0 | 6 | 0 | 0 | 0 | +| (gen_demux.i_w_fifo) | fifo_v3 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam | 22 | 22 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_demux.i_w_spill_reg | spill_register__parameterized0 | 410 | 410 | 0 | 0 | 152 | 0 | 0 | 0 | +| spill_register_flushable_i | spill_register_flushable__parameterized0 | 410 | 410 | 0 | 0 | 152 | 0 | 0 | 0 | +| gen_slv_port_demux[1].i_axi_err_slv | axi_err_slv_13 | 100 | 84 | 16 | 0 | 46 | 0 | 0 | 0 | +| (gen_slv_port_demux[1].i_axi_err_slv) | axi_err_slv_13 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| i_atop_filter | axi_atop_filter | 44 | 44 | 0 | 0 | 19 | 0 | 0 | 0 | +| (i_atop_filter) | axi_atop_filter | 32 | 32 | 0 | 0 | 17 | 0 | 0 | 0 | +| r_resp_cmd | stream_register | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_fifo | fifo_v2 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized0 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_b_fifo | fifo_v3__parameterized2 | 10 | 6 | 4 | 0 | 4 | 0 | 0 | 0 | +| (i_b_fifo) | fifo_v3__parameterized2 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized2 | 6 | 2 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_r_counter | counter | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_counter | delta_counter__parameterized0 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | +| i_r_fifo | fifo_v3__parameterized3 | 17 | 9 | 8 | 0 | 7 | 0 | 0 | 0 | +| (i_r_fifo) | fifo_v3__parameterized3 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized3 | 10 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | +| i_w_fifo | fifo_v3__parameterized1 | 18 | 14 | 4 | 0 | 7 | 0 | 0 | 0 | +| (i_w_fifo) | fifo_v3__parameterized1 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | +| gen_fpga_queue.fifo_ram | AsyncDpRam__parameterized1 | 11 | 7 | 4 | 0 | 0 | 0 | 0 | 0 | +| i_bootrom | bootrom_32 | 65 | 65 | 0 | 0 | 9 | 2 | 0 | 0 | +| i_clint | clint | 182 | 182 | 0 | 0 | 153 | 0 | 0 | 0 | +| (i_clint) | clint | 32 | 32 | 0 | 0 | 129 | 0 | 0 | 0 | +| axi_lite_interface_i | axi_lite_interface | 150 | 150 | 0 | 0 | 21 | 0 | 0 | 0 | +| i_sync_edge | clint_sync_wedge | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | +| (i_sync_edge) | clint_sync_wedge | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| i_sync | clint_sync | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | +| i_dm_axi2mem | axi2mem | 387 | 387 | 0 | 0 | 65 | 0 | 0 | 0 | +| i_dm_axi_master | axi_adapter | 71 | 71 | 0 | 0 | 44 | 0 | 0 | 0 | +| i_dm_top | dm_top | 497 | 497 | 0 | 0 | 613 | 0 | 0 | 0 | +| i_dm_csrs | dm_csrs | 363 | 363 | 0 | 0 | 535 | 0 | 0 | 0 | +| (i_dm_csrs) | dm_csrs | 243 | 243 | 0 | 0 | 531 | 0 | 0 | 0 | +| i_fifo | fifo_v2__parameterized0 | 120 | 120 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_fifo_v3 | fifo_v3__parameterized5 | 120 | 120 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_dm_mem | dm_mem | 94 | 94 | 0 | 0 | 75 | 0 | 0 | 0 | +| (i_dm_mem) | dm_mem | 8 | 8 | 0 | 0 | 70 | 0 | 0 | 0 | +| gen_rom_snd_scratch.i_debug_rom | debug_rom | 86 | 86 | 0 | 0 | 5 | 0 | 0 | 0 | +| i_dm_sba | dm_sba | 40 | 40 | 0 | 0 | 3 | 0 | 0 | 0 | +| i_dmi_jtag | dmi_jtag | 490 | 490 | 0 | 0 | 340 | 0 | 0 | 0 | +| (i_dmi_jtag) | dmi_jtag | 1 | 1 | 0 | 0 | 84 | 0 | 0 | 0 | +| i_dmi_cdc | dmi_cdc | 365 | 365 | 0 | 0 | 164 | 0 | 0 | 0 | +| i_cdc_req | cdc_2phase | 322 | 322 | 0 | 0 | 89 | 0 | 0 | 0 | +| i_dst | cdc_2phase_dst | 319 | 319 | 0 | 0 | 45 | 0 | 0 | 0 | +| i_src | cdc_2phase_src | 3 | 3 | 0 | 0 | 44 | 0 | 0 | 0 | +| i_cdc_resp | cdc_2phase__parameterized0 | 43 | 43 | 0 | 0 | 75 | 0 | 0 | 0 | +| i_dst | cdc_2phase_dst__parameterized0 | 39 | 39 | 0 | 0 | 38 | 0 | 0 | 0 | +| i_src | cdc_2phase_src__parameterized0 | 4 | 4 | 0 | 0 | 37 | 0 | 0 | 0 | +| i_dmi_jtag_tap | dmi_jtag_tap | 124 | 124 | 0 | 0 | 92 | 0 | 0 | 0 | +| i_rstgen_main | rstgen | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_rstgen_bypass | rstgen_bypass | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_xlnx_blk_mem_gen | xlnx_blk_mem_gen | 358 | 353 | 4 | 1 | 125 | 48 | 0 | 0 | +| (i_xlnx_blk_mem_gen) | xlnx_blk_mem_gen | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| U0 | xlnx_blk_mem_gen_blk_mem_gen_v8_4_7 | 358 | 353 | 4 | 1 | 125 | 48 | 0 | 0 | +| (U0) | xlnx_blk_mem_gen_blk_mem_gen_v8_4_7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst_blk_mem_gen | xlnx_blk_mem_gen_blk_mem_gen_v8_4_7_synth | 358 | 353 | 4 | 1 | 125 | 48 | 0 | 0 | +| gnbram.gaxibmg.axi_blk_mem_gen | xlnx_blk_mem_gen_blk_mem_gen_top | 135 | 134 | 0 | 1 | 13 | 48 | 0 | 0 | +| valid.cstr | xlnx_blk_mem_gen_blk_mem_gen_generic_cstr | 135 | 134 | 0 | 1 | 13 | 48 | 0 | 0 | +| has_mux_b.B | xlnx_blk_mem_gen_blk_mem_gen_mux__parameterized0 | 128 | 128 | 0 | 0 | 3 | 0 | 0 | 0 | +| ramloop[0].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| (ramloop[0].ram.r) | xlnx_blk_mem_gen_blk_mem_gen_prim_width | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[10].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[11].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[12].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized11 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized11 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[13].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized12 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized12 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[14].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized13 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized13 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[15].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized14 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized14 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[16].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized15 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized15 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[17].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized16 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized16 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[18].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized17 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized17 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[19].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized18 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized18 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[1].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[20].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized19 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized19 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[21].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized20 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized20 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[22].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized21 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized21 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[23].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized22 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized22 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[24].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized23 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized23 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[25].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized24 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized24 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[26].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized25 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized25 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[27].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized26 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized26 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[28].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized27 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized27 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[29].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized28 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized28 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[2].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[30].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized29 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized29 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[31].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized30 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized30 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[32].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized31 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized31 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[33].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized32 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized32 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[34].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized33 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized33 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[35].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized34 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized34 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[36].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized35 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized35 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[37].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized36 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized36 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[38].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized37 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized37 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[39].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized38 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized38 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[3].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized2 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized2 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[40].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized39 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized39 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[41].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized40 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized40 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[42].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized41 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized41 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[43].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized42 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized42 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[44].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized43 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized43 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[45].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized44 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized44 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[46].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized45 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| (ramloop[46].ram.r) | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized45 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized45 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[47].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized46 | 7 | 6 | 0 | 1 | 8 | 1 | 0 | 0 | +| (ramloop[47].ram.r) | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized46 | 5 | 4 | 0 | 1 | 8 | 0 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized46 | 2 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[4].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized3 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized3 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[5].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized4 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized4 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[6].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized5 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized5 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[7].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized6 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized6 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[8].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized7 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized7 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| ramloop[9].ram.r | xlnx_blk_mem_gen_blk_mem_gen_prim_width__parameterized8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| prim_noinit.ram | xlnx_blk_mem_gen_blk_mem_gen_prim_wrapper__parameterized8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| gnbram.gaxibmg.axi_rd_sm | xlnx_blk_mem_gen_blk_mem_axi_read_wrapper | 122 | 122 | 0 | 0 | 56 | 0 | 0 | 0 | +| (gnbram.gaxibmg.axi_rd_sm) | xlnx_blk_mem_gen_blk_mem_axi_read_wrapper | 18 | 18 | 0 | 0 | 50 | 0 | 0 | 0 | +| axi_read_fsm | xlnx_blk_mem_gen_blk_mem_axi_read_fsm | 104 | 104 | 0 | 0 | 6 | 0 | 0 | 0 | +| gnbram.gaxibmg.axi_wr_fsm | xlnx_blk_mem_gen_blk_mem_axi_write_wrapper | 101 | 97 | 4 | 0 | 56 | 0 | 0 | 0 | +| (gnbram.gaxibmg.axi_wr_fsm) | xlnx_blk_mem_gen_blk_mem_axi_write_wrapper | 45 | 41 | 4 | 0 | 52 | 0 | 0 | 0 | +| axi_wr_fsm | xlnx_blk_mem_gen_blk_mem_axi_write_fsm | 56 | 56 | 0 | 0 | 4 | 0 | 0 | 0 | +| i_xlnx_clk_gen | xlnx_clk_gen | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | xlnx_clk_gen_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 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